Patents by Inventor Yoshimi Hisatsune

Yoshimi Hisatsune has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Paste including a mixture of powders, connection plug, burying method, and semiconductor device manufacturing method
    Patent number: 7049223
    Abstract: Form a trench in a major surface of a semiconductor substrate, then bury a paste in the trench. The paste contains solids having a conductive substance and a resin, and solvent for dissolving the resin. The solids content of the paste is not less than 60 vol % and a viscosity ratio thereof is not more than 2.
    Type: Grant
    Filed: August 25, 2003
    Date of Patent: May 23, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keiichi Sasaki, Manabu Kimura, Yoshimi Hisatsune, Nobuo Hayasaka
  • Semiconductor device and method of manufacturing the same
    Patent number: 6828684
    Abstract: There is provided a semiconductor device including a semiconductor substrate and a conductive layer above the semiconductor substrate, wherein the conductive layer contains copper, a surface region of the conductive layer contains at least one of C—H bonds and C—C bonds, and a total amount of C atoms forming the C—H bonds and C atoms forming the C—C bonds in the surface region is 30 atomic % or more of a whole amount of elements in the surface region.
    Type: Grant
    Filed: March 21, 2003
    Date of Patent: December 7, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Ikegami, Rempei Nakata, Takashi Yoda, Nobuo Hayasaka, Yoshimi Hisatsune
  • Semiconductor device, its manufacturing process, position matching mark, pattern forming method and pattern forming device
    Patent number: 6709966
    Abstract: A semiconductor device comprising the bump containing magnetic body, magnetic body, the bump including non-magnetic body for at least partially covering the magnetic body, mixture of magnetic particles and non-magnetic particles and the bump including baked magnetic particles and baked non-magnetic particles.
    Type: Grant
    Filed: June 29, 2000
    Date of Patent: March 23, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshimi Hisatsune, Keiichi Sasaki, Hiroshi Ikegami, Mie Matsuo, Nobuo Hayasaka, Katsuya Okumura
  • Paste including a mixture of powders, connection plug, burying method, and semiconductor device manufacturing method
    Publication number: 20040043596
    Abstract: Form a trench in a major surface of a semiconductor substrate, then bury a paste in the trench. The paste contains solids having a conductive substance and a resin, and solvent for dissolving the resin. The solids content of the paste is not less than 60 vol % and a viscosity ratio thereof is not more than 2.
    Type: Application
    Filed: August 25, 2003
    Publication date: March 4, 2004
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Keiichi Sasaki, Manabu Kimura, Yoshimi Hisatsune, Nobuo Hayasaka
  • Paste including a mixture of powders, connection plug, burying method, and semiconductor device manufacturing method
    Patent number: 6657306
    Abstract: Form a trench in a major surface of a semiconductor substrate, then bury a paste in the trench. The paste contains solids having a conductive substance and a resin, and solvent for dissolving the resin. The solids content of the paste is not less than 60 vol % and a viscosity ratio thereof is not more than 2.
    Type: Grant
    Filed: November 28, 2000
    Date of Patent: December 2, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keiichi Sasaki, Manabu Kimura, Yoshimi Hisatsune, Nobuo Hayasaka
  • Semiconductor device and method of manufacturing the same
    Publication number: 20030181041
    Abstract: There is provided a semiconductor device including a semiconductor substrate and a conductive layer above the semiconductor substrate, wherein the conductive layer contains copper, a surface region of the conductive layer contains at least one of C—H bonds and C—C bonds, and a total amount of C atoms forming the C—H bonds and C atoms forming the C—C bonds in the surface region is 30 atomic % or more of a whole amount of elements in the surface region.
    Type: Application
    Filed: March 21, 2003
    Publication date: September 25, 2003
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Ikegami, Rempei Nakata, Takashi Yoda, Nobuo Hayasaka, Yoshimi Hisatsune
  • Semiconductor device and method of manufacturing the same
    Patent number: 6566261
    Abstract: There is provided a semiconductor device including a semiconductor substrate and a conductive layer above the semiconductor substrate, wherein the conductive layer contains copper, a surface region of the conductive layer contains at least one of C—H bonds and C—C bonds, and a total amount of C atoms forming the C—H bonds and C atoms forming the C—C bonds in the surface region is 30 atomic % or more of a whole amount of elements in the surface region.
    Type: Grant
    Filed: September 6, 2001
    Date of Patent: May 20, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Ikegami, Rempei Nakata, Takashi Yoda, Nobuo Hayasaka, Yoshimi Hisatsune
  • Semiconductor device and method of manufacturing the same
    Publication number: 20020050647
    Abstract: There is provided a semiconductor device including a semiconductor substrate and a conductive layer above the semiconductor substrate, wherein the conductive layer contains copper, a surface region of the conductive layer contains at least one of C—H bonds and C—C bonds, and a total amount of C atoms forming the C—H bonds and C atoms forming the C—C bonds in the surface region is 30 atomic % or more of a whole amount of elements in the surface region.
    Type: Application
    Filed: September 6, 2001
    Publication date: May 2, 2002
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroshi Ikegami, Rempei Nakata, Takashi Yoda, Nobuo Hayasaka, Yoshimi Hisatsune