Abstract: The configuration of a microcomputer to be used as the control device of a medium reading apparatus is such that writing unit by unit into and erasion block by block from a prescribed area, such as a user data storage area, in a nonvolatile memory built into the microcomputer makes possible, if any writing into the user data storage area is needed, for data to be successively written while updating the units, data included in the prescribed area to be erased when all the units have been written into, and the next data to be written into the erased blocks.

Abstract: There is provided an information recording/recording device that can easily modify the respective reproduction control programs and other programs of plural disk drive units simply by mounting an information recording medium in one disk drive unit. One disk drive unit uses predetermined recording information of a mounted information recording medium to rewrite a program stored in a nonvolatile memory of the one disk drive unit, and transfers a program to another disk drive unit over an interface bus to instruct program rewriting. According to the rewriting instruction from the one disk drive unit, the other disk drive unit rewrites a program stored in a nonvolatile memory thereof. If the information recording medium is reproduced in one disk drive unit, program information can be transferred to a different disk drive unit.

Abstract: There is provided an information recording/recording device that can easily modify the respective reproduction control programs and other programs of plural disk drive units simply by mounting an information recording medium in one disk drive unit. One disk drive unit uses predetermined recording information of a mounted information recording medium to rewrite a program stored in a nonvolatile memory of the one disk drive unit, and transfers a program to another disk drive unit over an interface bus to instruct program rewriting. According to the rewriting instruction from the one disk drive unit, the other disk drive unit rewrites a program stored in a nonvolatile memory thereof. If the information recording medium is reproduced in one disk drive unit, program information can be transferred to a different disk drive unit.

Abstract: The configuration of a microcomputer to be used as the control device of a medium reading apparatus is such that writing unit by unit into and erasion block by block from a prescribed area, such as a user data storage area, in a nonvolatile memory built into the microcomputer makes possible, if any writing into the user data storage area is needed, for data to be successively written while updating the units, data included in the prescribed area to be erased when all the units have been written into, and the next data to be written into the erased blocks.

Abstract: An apparatus for reproducing recorded information reads information from the track surface of a CD-ROM disk 1, performs error detection and correction processing on the read information to reproduce recorded information and then outputs the reproduced information. This apparatus includes a control device 11, which switches a reproduction operation to the standard speed mode in response to a correction failure condition generated in the quadruple speed mode and retries standard-speed reading of the information read with an error uncorrectable in the quadruple speed mode. Reducing the signal read speed to one-fourth in the retry processing at the standard speed improves the C/N ratio of the high-frequency signal RF by 6 dB, which in turn improves the correction capability for random errors.

Abstract: A receiving circuit is designed for an MSK (Minimum Shift Keying) receiver and a QPSK (Quadrature Phase Shift Keying) receiver. The circuit provides a synchronous state determining device and a control voltage sweeping device for sweeping the output of a voltage oscillator. In the asynchronous state, a switch is turned off for interrupting a reproducing phase error signal so that the output of the voltage oscillator may be swept for causing the synchronous state. Then, the sweeping operation is stopped and the switch is turned on for controlling the voltage of the voltage controlled oscillator so that the low-frequency error component is removed from the phase error signal of the demodulating circuit. This results in implementing the simply-arranged demodulating circuit which keeps the proper demodulating performance against the shifted carrier frequency without any degrade and demodulates the input signal stably if the signal has a low C/N ratio.

Abstract: An offset compensation circuit for compensating a DC offset which occurs in a circuit line including an A/D converter or an A/D and D/A converter in which not only the polarity bit of digital data but also information concerning the amplitude of an analog input signal are applied to an integrator to precisely compensate an offset voltage in a circuit line. The level of a proper offset compensation voltage is provided even when an input analog signal such as a music signal is absent, and when an A/D and D/A converter is provided which can perform both A/D conversion and D/A conversion the DC offset can be precisely compensated shortly after the change of the mode from D/A conversion to A/D conversion.

Abstract: An integration type D/A and A/D converter having improved linearity and low power consumption. Logic circuits such as ECL counters consuming a major part of power of the D/A and A/D converters are realized through CMOS process. Current source circuits, current switch circuit and comparator circuit of the integration type A/D converter are realized in IC through bipolar process ensuring high accuracy and low noise. Logic parts such as counter is realized through CMOS process.

Abstract: In a disc playback apparatus using an optical pickup or the like, any flaws on a track of the disc are detected using: a first level detector for detecting a maximum value level of a recording information signal of an output of the pickup; a second level detector for detecting a change of the maximum value level of the recording information signal; and a comparator for comparing outputs of the above first and second level detectors. When any flaws are detected, a driving signal of a driving device for the pickup is held to a fixed reference potential.

Abstract: A reproducing rate control apparatus for an information recording disc in which pieces of information and absolute times for respective information pieces (representative of the reproduction time measured from the innermost circumference of the information recording disc) are recorded on the disc at a constant linear velocity, a revolution number of the disc at a command position is predicted, rotation of a disc drive motor is controlled so that the disc rotates at a predicted revolution number, and an information reader adapted to read the information recorded on the disc is moved to the command position when the revolution number controlling is effected or after the revolution number controlling has been completed.

Abstract: A digital-to-analogue converter for use in a digitally-recorded-signal reproducing apparatus comprises a first constant current source, a switch for allowing the constant current of the first constant current source to flow therethrough for a period corresponding to the digital data, a second constant current source generating a current flowing in the direction opposite to that of the current generated by the first constant current source, a switch for allowing the current of the second constant current source to flow therethrough for a predetermined constant period, and an integrator, wherein the sum of the first and second constant currents is integrated by the integrator. The analogue signal outputted by the integrator has a center level in the vicinity of the ground potential level.

Abstract: An information reproducing apparatus having a tracking servo control loop for causing an information reading unit including device for detecting a tracking error signal for tracking an information bearing track on a disc, to track the information bearing track in accordance with the tracking error signal so as to reproduce information in accordance with an information signal read by the information reading unit. A circuit for extracting a discrimination signal for discriminating a negative feedback region of the tracking error signal is provided so that a tracking servo control loop is closed in the negative feedback region.

Abstract: Disclosed is a disc or tape signal reproducing apparatus having a first speed control loop in which the duration of a specific pulse in the PCM signal recorded on the disc or tape is detected and the current sync signal interval is anticipated from the duration of the pulse so that the motor speed is pulled into the operation range of the sync signal detector, and a second speed control loop which controls the motor speed basing on the sync signal reproduced by the sync signal detector. The motor speed is controlled by the first speed control loop until the sync signal detector detects the sync signal, thereafter the motor speed is controlled by the second speed control loop basing on the reproduced sync signal.

Abstract: An improved antenna tuning circuit for a long and a medium wave AM radio receiver is disclosed. The antenna tuning circuit of the present invention comprises a tuning coil wound around a ferrite core, a variable capacitor connected in parallel with the tuning coil, and a field effect transistor. One end of the tuning coil is connected to the gate electrode directly or through an impedance means, while the other end of the tuning coil is grounded. The output signal of the antenna tuning circuit is taken out from a selected one of the source or drain electrode of the field effect transistor, whereby the signal to noise ratio may be remarkably improved.

Abstract: Signal transmitting operation is effected in a muting circuit when a first constant current source connected to the emitters of first and second transistors is operative with a second constant current source connected to the emitters of third and fourth transistors being inoperative. The signal transmitting operation is not effected in the opposite case. A bias resistor is interposed between the bases of the first and third transistors. To eliminate the popping noise when the power source is turned on, a switching element is connected parallel to the bias resistor and is kept in the ON state for a predetermined period of time after making of the power source.

Abstract: A stereo demodulation system for an FM stereo broadcast receiver having frequency dividing means receiving the output of the voltage controlled oscillator in the phase locked loop and producing the first and the second switching signals which are supplied to the first and the second switch and decoder circuit for switching and decoding the stereo composite signal, wherein said first and second switching signals are produced with the fixed phase relationship therebetween.

Abstract: In an FM receiver having an amplifier for amplifying an FM signal of intermediate frequency applied to an input terminal, and a phase multiplier type FM demodulator for demodulating the FM signal of intermediate frequency amplified by the amplifier, a noise muting circuit is disposed between the demodulator and the amplifier for muting noise transmitted from the amplifier to the demodulator when no FM signal input appears at the input terminal. This noise muting circuit comprises a pair of diodes connected in inverse-parallel with each other.

Abstract: A phase-shifting multiplication type FM demodulation circuits comprises a gate circuit including a first and a second switching circuit adapted to be switched for an FM intermediate frequency signal, a resonance circuit and a phase-shifting element. The FM intermediate frequency signal is phase-shifted for about .pi./2 (or 90.degree.) and the phase-shifted signal (frequency) is fed to the second switching circuit of the gate circuit after the phase-conversion of the phase-shifted FM signal by means of a phase-shifter device. The demodulation circuit further includes a bias resistor for the second switching circuit which resistor serves also as a resonance resistor of the resonance circuit, a substraction circuit for detecting output signal from the gate circuit, an output resistor for determining magnitude of the output signal from the subtraction circuit, and a lowpass filter for eliminating higher harmonics from the output signal appearing across the output resistor thereby producing a demodulated output.

Abstract: An integration type D/A and A/D converter having improved linearity and low power consumption. Logic circuits such as ECL counters consuming a major part of power of the D/A and A/D converters are realized through CMOS process. Current source circuits, current switch circuit and comparator circuit of the integration type A/D converter are realized in IC through bipolar process ensuring high accuracy and low noise. Logic parts such as counter is realized through CMOS process.