Abstract: An interface circuit capable of performing an exact data transfer between two devices operated by asynchronous two clocks of the same frequency even when the clock contains a jitter, including three-stage latches coupled by a cascade connection and a control circuit to output a one-shot pulse when one external clock and one internal clock are input. The first latch latches input data by the external clock, the second latch latches the data output from the first latch by the pulse of the control circuit, and the third latch latches the data output from the second latch by the internal clock and outputs the data. The input data are output from the third latch in the input order without a continuous or repeated output of the same data or an omission or deletion of the output data.