Abstract: An information processing device includes a CPU, a ROM that stores an execution code executed by the CPU, an address management memory that stores address information relating to a code read from the CPU, and a patch code memory that stores a patch code that corrects the execution code. The address information includes an address of the patch code memory where the patch code is stored instead of an address of the ROM where the execution code that is replaced by the patch code is stored. The CPU performs a process corresponding to the code read from the ROM or the patch code memory based on the address information stored in the address management memory.

Abstract: A data transfer control device including: a buffer controller which allocates a plurality of pipe regions in a packet buffer and controls access to the packet buffer; and a transfer controller which controls data transfer between the pipe regions and corresponding endpoints. The transfer controller performs processing of pausing data transfer between the pipe regions and the endpoints, the buffer controller performs reconstruction processing which includes at least one of deletion, addition, and size change of the pipe regions after the completion of the pause processing, and then the transfer controller resumes the paused data transfer after the reconstruction processing of the pipe regions. Data in the pipe regions before the reconstruction processing is copied to the pipe regions after the reconstruction processing while preventing the data from being erased.

Abstract: Data to be transferred from a BUS1 (IEEE 1394 or USB) is encrypted by a second encryption process (DES) and the encrypted data is written to an external SDRAM through an external terminal of a data transfer control device. The encrypted data that has been written to the SDRAM is read through the external terminal, and the thus-read encrypted data is transferred to a BUS2 to which an HDD is connected. Encrypted data transferred from the BUS1 is decrypted by a first decryption process (DTCP), and is written to a small-capacity SRAM within the data transfer control device. The thus-written decrypted data is read from the SRAM and encrypted by the second encryption process. Paths that bypass the second encryption (or decryption) are also provided.

Abstract: A data transfer control device includes a DMAC1 that writes a packet transferred from a BUS1 (IEEE 1394 or USB), to a SRAM, a DMAC2 that reads the written isochronous data from the SRAM and writes it to a SDRAM, and a DMAC3 that reads the written isochronous data and transfers it to a BUS2 side. During transmission, isochronous data is read from the SDRAM and written to SRAM, and an isochronous packet including the written isochronous data is transferred to the BUS1 side. The SRAM includes an isochronous data area and an asynchronous data area. The SRAM is provided insides the data transfer control device and the SDRAM is provided on outside the data transfer control device.

Abstract: A processing section reserves a number of transfers for an isochronous packet which includes isochronous data in an transfer number reservation register TNREG. A DMAC1 reads that isochronous packet from SRAM, and the thus-read isochronous packet is transferred automatically to a BUS1 (IEEE 1394 or USB) side at each isochronous transfer cycle until the number of transfers reserved in TNREG reaches zero. An SRAM header area is divided into page K and page L areas, and registers TNREGK and TNREGL are provided for reserving a number of transfers for each of the page K and L areas. During a special reproduction, a data pointer is used to select a TS packet which includes an I picture, for automatic transfer to the BUS1 side.

Abstract: A data transfer control device including: a buffer controller which allocates a plurality of pipe regions in a packet buffer and controls access to the packet buffer; and a transfer controller which controls data transfer between the pipe regions and corresponding endpoints. The transfer controller performs processing of pausing data transfer between the pipe regions and the endpoints, the buffer controller performs reconstruction processing which includes at least one of deletion, addition, and size change of the pipe regions after the completion of the pause processing, and then the transfer controller resumes the paused data transfer after the reconstruction processing of the pipe regions. Data in the pipe regions before the reconstruction processing is copied to the pipe regions after the reconstruction processing while preventing the data from being erased.

Abstract: A semiconductor device in which internal data, programs or program instructions can be read when a predetermined data or signal is inputted. It is equipped with protect circuits 31-34 that are connected between a CPU 11, and ROM 21, a RAM 22, a register 23 and a user circuit 24, respectively; a debug circuit 12 that, when connected to a debug tool 40, controls the CPU 11 and instructs the protect circuits 31-34 not to transfer data, and a protect release circuit 13 that, upon receiving a predetermined signal, instructs the protect circuits 31-34 to transfer data without regard to an instruction from the debug circuit 12. The CPU 11 executes predetermined operations when it is not connected to the debug tool 40.

Abstract: Data to be transferred from a BUS1 (IEEE 1394 or USB) is encrypted by a second encryption process (DES) and the encrypted data is written to an external SDRAM through an external terminal of a data transfer control device. The encrypted data that has been written to the SDRAM is read through the external terminal, and the thus-read encrypted data is transferred to a BUS2 to which an HDD is connected. Encrypted data transferred from the BUS1 is decrypted by a first decryption process (DTCP), and is written to a small-capacity SRAM within the data transfer control device. The thus-written decrypted data is read from the SRAM and encrypted by the second encryption process. Paths that bypass the second encryption (or decryption) are also provided.

Abstract: Messy and lots of questionable computer numbers in this, During reception, data to be transferred from a BUS1 (IEEE 1394 or USB) side is written into a reception data in SRAM, and, if the quantity of reception data exceeds a transfer unit ATU, data is read from the reception data area and transferred to a BUS2 side. During transmission, data transferred from the BUS2 side is written into a transmission data area in SRAM, and, when there is an instruction from a processing section (CPU) to start transmission (reservation of a number of transfers), the data that has been written into the transmission data area in SRAM is read and transferred to the BUS1 side. The size of the reception data area is smaller than that of the transmission data area. The transfer unit ATU is set to be equal to an encryption unit of a circuit (DES) that encrypts data read from the SRAM.

Abstract: A processing section reserves a number of transfers for an isochronous packet which includes isochronous data in an transfer number reservation register TNREG. A DMAC1 reads that isochronous packet from SRAM, and the thus-read isochronous packet is transferred automatically to a BUS1 (IEEE 1394 or USB) side at each isochronous transfer cycle until the number of transfers reserved in TNREG reaches zero. An SRAM header area is divided into page K and page L areas, and registers TNREGK and TNREGL are provided for reserving a number of transfers for each of the page K and L areas. During a special reproduction, a data pointer is used to select a TS packet which includes an I picture, for automatic transfer to the BUS1 side.

Abstract: A data transfer control device includes a DMAC1 that writes a packet transferred from a BUS1 (IEEE 1394 or USB), to a SRAM, a DMAC2 that reads the written isochronous data from the SRAM and writes it to a SDRAM, and a DMAC3 that reads the written isochronous data and transfers it to a BUS2 side. During transmission, isochronous data is read from the SDRAM and written to SRAM, and an isochronous packet including the written isochronous data is transferred to the BUS1 side. The SRAM includes an isochronous data area and an asynchronous data area. The SRAM is provided insides the data transfer control device and the SDRAM is provided on outside the data transfer control device.