Patents by Inventor Yoshimi Uda

Yoshimi Uda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6720120
    Abstract: A substrate includes fine lines. The fine lines are obtained according to a fine-line forming process, which includes a process of projecting light from above the substrate onto predetermined regions on a photosensitive material provided on the substrate and a developing process after the light projection process. A narrow-width portion is provided at an end portion of each of the fine lines in a longitudinal direction of the fine line. The width of the narrow-width portion is smaller than the width of a portion adjacent to the narrow-width portion.
    Type: Grant
    Filed: December 6, 2001
    Date of Patent: April 13, 2004
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yoshimi Uda, Kazuya Ishiwata, Shinsaku Kubo, Yasuyuki Watanabe
  • Publication number: 20040027054
    Abstract: As a substrate having a fine line and capable of suppressing crack generation in the substrate and peeling of the fine line, the invention discloses a configuration in which plural recesses are arranged on the fine line, and particularly a configuration in which the interval of the plural recesses does not exceed 200 &mgr;m. There is also disclosed a configuration in which the plural recesses are arranged along a direction crossing the longitudinal direction of the fine line.
    Type: Application
    Filed: August 11, 2003
    Publication date: February 12, 2004
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Yoshimi Uda, Kazuya Ishiwata, Shinsaku Kubo, Yasuyuki Watanabe
  • Patent number: 6653232
    Abstract: A method of manufacturing wiring includes a step of forming a conductive layer pattern through a developing step after performing film formation and exposure step using photosensitive paste that contains a photosensitive material and a conductive material, a step of forming an insulating layer pattern through a developing step after performing film formation and exposure step using photosensitive paste that contains a photosensitive material and an insulating material, and a baking step for baking the conductive layer pattern and the insulating layer pattern. Thus, a wiring pattern can be formed with high precision by reducing an edge curl.
    Type: Grant
    Filed: July 31, 2002
    Date of Patent: November 25, 2003
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yoshimi Uda, Kazuya Ishiwata
  • Patent number: 6621207
    Abstract: As a substrate having a fine line and capable of suppressing crack generation in the substrate and peeling of the fine line, the invention discloses a configuration in which plural recesses are arranged on the fine line, and particularly a configuration in which the interval of the plural recesses does not exceed 200 &mgr;m. There is also disclosed a configuration in which the plural recesses are arranged along a direction crossing the longitudinal direction of the fine line.
    Type: Grant
    Filed: December 14, 2001
    Date of Patent: September 16, 2003
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yoshimi Uda, Kazuya Ishiwata, Shinsaku Kubo, Yasuyuki Watanabe
  • Publication number: 20030049572
    Abstract: A method for forming patterned insulating elements on a substrate includes a plurality of exposure steps of exposing a photosensitive paste provided on the substrate through at least one mask having a predetermined pattern; a developing step of developing the exposed photosensitive paste to form a precursor pattern; and a firing step of firing the precursor pattern to form the patterned insulating elements. This method is applied to a method for forming an electron source and a method for forming an image display device including the electron source.
    Type: Application
    Filed: September 6, 2002
    Publication date: March 13, 2003
    Inventors: Yasuyuki Watanabe, Kazuya Ishiwata, Yoshimi Uda, Shinsaku Kubo
  • Publication number: 20030030357
    Abstract: In an electron source having an electron emitting member, the electron emitting member is connected to a first or second conductive member by a third conductive member which is connected to the first or second conductive member through an aperture forming in an insulating member, and such aperture has such a shape as to become narrower from an end of the third conductive member toward the other end. Such configuration avoids that the third conductive member is damaged in the connecting portion with the first or second conductive member by the thermal stress therein.
    Type: Application
    Filed: July 31, 2002
    Publication date: February 13, 2003
    Inventors: Hiroaki Toshima, Kazuya Ishiwata, Yoshimi Uda
  • Publication number: 20030027417
    Abstract: A method of manufacturing wiring includes a step of forming a conductive layer pattern through a developing step after performing film formation and exposure step using photosensitive paste that contains a photosensitive material and a conductive material, a step of forming an insulating layer pattern through a developing step after performing film formation and exposure step using photosensitive paste that contains a photosensitive material and an insulating material, and a baking step for baking the conductive layer pattern and the insulating layer pattern. Thus, a wiring pattern can be formed with high precision by reducing an edge curl.
    Type: Application
    Filed: July 31, 2002
    Publication date: February 6, 2003
    Inventors: Yoshimi Uda, Kazuya Ishiwata
  • Publication number: 20020100913
    Abstract: As a substrate having a fine line and capable of suppressing crack generation in the substrate and peeling of the fine line, the invention discloses a configuration in which plural recesses are arranged on the fine line, and particularly a configuration in which the interval of the plural recesses does not exceed 200 &mgr;m. There is also disclosed a configuration in which the plural recesses are arranged along a direction crossing the longitudinal direction of the fine line.
    Type: Application
    Filed: December 14, 2001
    Publication date: August 1, 2002
    Inventors: Yoshimi Uda, Kazuya Ishiwata, Shinsaku Kubo, Yasuyuki Watanabe
  • Publication number: 20020095785
    Abstract: The wirings on an electron source substrate are formed to intersect with each other in a matrix so as to address the electron emission devices on the substrate. First and second wirings intersect with each other on a crossing point. As such a crossing point, an insulating layer is placed between the first and second wirings. To ensure insulation, a plurality of insulating layers are laminated. According to the present invention, a wiring pattern is provided on the substrate with a conductive paste and baking the wiring pattern of the conductive paste to form the first wiring. Subsequently part of the first wiring is coated at the crossing point with an insulating paste and baking the insulating paste to form a first insulating layer. The coating thickness of the insulating layer formed adjacent to sidewalls of the crossing point is substanially equal to the height of the first wiring.
    Type: Application
    Filed: December 11, 2001
    Publication date: July 25, 2002
    Inventors: Shinsaku Kubo, Kazuya Ishiwata, Yoshimi Uda, Yasuyuki Watanabe, Hiroaki Toshima
  • Publication number: 20020074557
    Abstract: A substrate includes fine lines. The fine lines are obtained according to a fine-line forming process, which includes a process of projecting light from above the substrate onto predetermined regions on a photosensitive material provided on the substrate and a developing process after the light projection process. A narrow-width portion is provided at an end portion of each of the fine lines in a longitudinal direction of the fine line. The width of the narrow-width portion is smaller than the width of a portion adjacent to the narrow-width portion.
    Type: Application
    Filed: December 6, 2001
    Publication date: June 20, 2002
    Inventors: Yoshimi Uda, Kazuya Ishiwata, Shinsaku Kubo, Yasuyuki Watanabe
  • Publication number: 20020031728
    Abstract: In a method of manufacturing an electroconductive film, a developing process is implemented on a photosensitive paste layer (12) having a height of about 13 &mgr;m in a state where exposure is repeated twice in FIG. 1D, and thereafter, a baking process is completed to form a wiring pattern (20). As a result, the curling of an edge formed in the wiring pattern (20) can be remarkably reduced.
    Type: Application
    Filed: September 14, 2001
    Publication date: March 14, 2002
    Inventors: Yoshimi Uda, Kazuya Ishiwata, Shinsaku Kubo, Yasuyuki Watanabe