Patents by Inventor Yoshimi Yamashita
Yoshimi Yamashita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11912888Abstract: A fluoropolyether group-containing compound represented by formula (1) or (2) below: wherein RSi is represented by formula (Si), and the symbols are as defined in the description —X1—SiRa1p1Rb1q1Rc1r1??(S1).Type: GrantFiled: September 20, 2021Date of Patent: February 27, 2024Assignee: DAIKIN INDUSTRIES, LTD.Inventors: Tsuneo Yamashita, Hisashi Mitsuhashi, Kenichi Katsukawa, Takeshi Maehira, Yoshimi Motonari
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Patent number: 9125811Abstract: A nanofiber laminate sheet including a layer of a nanofiber of a water insoluble polymer and a layer of a water soluble polymer containing a cosmetic component or a medicinal component. The nanofiber is preferably colored. The layer of a water soluble polymer is preferably a layer of a nanofiber of the water soluble polymer containing the cosmetic component or the medicinal component. The nanofiber laminate sheet is suited for use as a cosmetic sheet for makeup.Type: GrantFiled: June 28, 2011Date of Patent: September 8, 2015Assignee: KAO CORPORATIONInventors: Takehiko Tojo, Masataka Ishikawa, Ritsuko Yamazaki, Yuko Yago, Motoaki Ito, Yoshimi Yamashita
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Patent number: 8642172Abstract: A nanofiber sheet including a nanofiber layer containing a polymeric nanofiber, a surface of nanofiber sheet being adhesive. The nanofiber preferably contains an adhesive component and a water insoluble polymer. The nanofiber sheet preferably has a water soluble layer containing a nanofiber containing a water soluble adhesive component and a water insoluble layer containing a nanofiber containing a water insoluble polymer laminated to each other. The nanofiber sheet preferably further includes a base layer located on one side of the nanofiber layer and an adhesive layer located on the other side of the nanofiber layer.Type: GrantFiled: December 25, 2009Date of Patent: February 4, 2014Assignee: Kao CorporationInventors: Takehiko Tojo, Masataka Ishikawa, Yoshimi Yamashita
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Patent number: 8501665Abstract: The present invention provides a method for manufacturing a film catalyst, including forming a catalyst layer on one side or each side of a base material to obtain a film catalyst, bending the film catalyst, and optionally cutting the film catalyst, wherein the bending step is conducted by bending the film catalyst with a bending tool composed of two gears that are oppositely arranged as meshing each other while a protective material having a compressibility of 40 to 95% is inserted between the catalyst layer of the film catalyst and the two gears.Type: GrantFiled: April 3, 2009Date of Patent: August 6, 2013Assignee: Kao CorporationInventors: Kunio Matsui, Masayasu Sato, Yoshimi Yamashita
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Publication number: 20130142852Abstract: A nanofiber laminate sheet including a layer of a nanofiber of a water insoluble polymer and a layer of a water soluble polymer containing a cosmetic component or a medicinal component. The nanofiber is preferably colored. The layer of a water soluble polymer is preferably a layer of a nanofiber of the water soluble polymer containing the cosmetic component or the medicinal component. The nanofiber laminate sheet is suited for use as a cosmetic sheet for makeup.Type: ApplicationFiled: June 28, 2011Publication date: June 6, 2013Applicant: KAO CORPORATIONInventors: Takehiko Tojo, Masataka Ishikawa, Ritsuko Yamazaki, Yuko Yago, Motoaki Ito, Yoshimi Yamashita
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Publication number: 20130125912Abstract: A nanofiber 10 made of a water soluble polymer, having a cavity 13, and containing an oily component 14 in the cavity 13. The nanofiber 10 preferably has a small-diametered portion 12 and a large-diametered portion 11. The cavity 13 is preferably in the large-diametered portion 11. The cavity 13 is also preferably in both the large-diametered portion 11 and the small-diametered portion 12, with the cavity 13 in the large-diametered portion 11 and the cavity 13 in the small-diametered portion 12 being interconnected.Type: ApplicationFiled: June 28, 2011Publication date: May 23, 2013Applicant: KAO CORPORATIONInventors: Takehiko Tojo, Yoshimi Yamashita, Masataka Ishikawa, Mika Shuin, Shinnosuke Uno
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Publication number: 20110259518Abstract: A nanofiber sheet including a nanofiber layer containing a polymeric nanofiber, a surface of nanofiber sheet being adhesive. The nanofiber preferably contains an adhesive component and a water insoluble polymer. The nanofiber sheet preferably has a water soluble layer containing a nanofiber containing a water soluble adhesive component and a water insoluble layer containing a nanofiber containing a water insoluble polymer laminated to each other. The nanofiber sheet preferably further includes a base layer located on one side of the nanofiber layer and an adhesive layer located on the other side of the nanofiber layer.Type: ApplicationFiled: December 25, 2009Publication date: October 27, 2011Applicant: KAO CORPORATIONInventors: Takehiko Tojo, Masataka Ishikawa, Yoshimi Yamashita
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Patent number: 7910955Abstract: A channel layer (11) made of compound semiconductor and a barrier layer (12) made of compound semiconductor having a band gap wider than the channel layer are formed over a substrate. A gate insulating film (13) made of first insulating material is formed on the barrier layer over the channel region. A gate electrode (23) is formed on a partial area of the gate insulating film. A protective film is disposed on the gate insulating film on both sides of the gate electrode. The protective film comprises a lower protective film (14) made of second insulating material whose etching resistance is different from the first insulating material and an upper protective film (15) made of third insulating film whose etching resistance is different from the second insulating material. A source electrode and a drain electrode are electrically connected to the channel layer on both sides of the gate electrode.Type: GrantFiled: July 17, 2007Date of Patent: March 22, 2011Assignee: Fujitsu LimitedInventors: Akira Endoh, Yoshimi Yamashita
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Publication number: 20110065569Abstract: The present invention provides a method for manufacturing a film catalyst, including forming a catalyst layer on one side or each side of a base material to obtain a film catalyst, bending the film catalyst, and optionally cutting the film catalyst, wherein the bending step is conducted by bending the film catalyst with a bending tool composed of two gears that are oppositely arranged as meshing each other while a protective material having a compressibility of 40 to 95% is inserted between the catalyst layer of the film catalyst and the two gears.Type: ApplicationFiled: April 3, 2009Publication date: March 17, 2011Applicant: KAO CORPORATIONInventors: Kunio Matsui, Masayasu Sato, Yoshimi Yamashita
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Publication number: 20070267655Abstract: A channel layer (11) made of compound semiconductor and a barrier layer (12) made of compound semiconductor having a band gap wider than the channel layer are formed over a substrate. A gate insulating film (13) made of first insulating material is formed on the barrier layer over the channel region. A gate electrode (23) is formed on a partial area of the gate insulating film. A protective film is disposed on the gate insulating film on both sides of the gate electrode. The protective film comprises a lower protective film (14) made of second insulating material whose etching resistance is different from the first insulating material and an upper protective film (15) made of third insulating film whose etching resistance is different from the second insulating material. A source electrode and a drain electrode are electrically connected to the channel layer on both sides of the gate electrode.Type: ApplicationFiled: July 17, 2007Publication date: November 22, 2007Applicant: FUJITSU LIMITEDInventors: Akira Endoh, Yoshimi Yamashita
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Patent number: 7019336Abstract: In a nitride-system semiconductor, being different from GaAs and Si, Schottky barrier heights ?B change significantly against work functions ?M of metals. Then, for example, on an HEMT in which a buffer layer and a barrier layer constituted by nitride-system semiconductors are sequentially formed on a substrate, and a gate electrode is formed on the barrier layer, when a metal having a relatively large work function ?M is selected as a metal constituting the gate electrode, and the thickness of the barrier layer is adjusted so that the Schottky barrier height ?B becomes larger as compared to a semiconductor surface potential ?S on both sides of the gate electrode, a two-dimensional electron gas cannot exist below the gate electrode even when no recess is formed on a portion immediately beneath the gate electrode on the barrier layer, so that the enhancement operation becomes possible.Type: GrantFiled: June 21, 2004Date of Patent: March 28, 2006Assignee: Fujitsu LimitedInventors: Yoshimi Yamashita, Akira Endoh, Keiji Ikeda
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Publication number: 20050280027Abstract: A first film of rare-earth metal is formed on a semiconductor region of compound semiconductor exposed on a substrate. A second film essentially comprising silicon is formed on the surface of the first film. The first and second films are heated to silicidate at least a portion of the first film in contact with the second film. It is possible to lower the contact resistance of an ohmic electrode formed on semiconductor having a wide band gap.Type: ApplicationFiled: July 20, 2005Publication date: December 22, 2005Applicant: FUJITSU LIMITEDInventors: Keiji Ikeda, Yoshimi Yamashita
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Patent number: 6936487Abstract: A first film of rare-earth metal is formed on a semiconductor region of compound semiconductor exposed on a substrate. A second film essentially comprising silicon is formed on the surface of the first film. The first and second films are heated to silicidate at least a portion of the first film in contact with the second film. It is possible to lower the contact resistance of an ohmic electrode formed on semiconductor having a wide band gap.Type: GrantFiled: May 6, 2003Date of Patent: August 30, 2005Assignee: Fujitsu LimitedInventors: Keiji Ikeda, Yoshimi Yamashita
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Publication number: 20050059197Abstract: In a nitride-system semiconductor, being different from GaAs and Si, Schottky barrier heights ?B change significantly against work functions ?M of metals. Then, for example, on an HEMT in which a buffer layer and a barrier layer constituted by nitride-system semiconductors are sequentially formed on a substrate, and a gate electrode is formed on the barrier layer, when a metal having a relatively large work function ?M is selected as a metal constituting the gate electrode, and the thickness of the barrier layer is adjusted so that the Schottky barrier height ?B becomes larger as compared to a semiconductor surface potential ?S on both sides of the gate electrode, a two-dimensional electron gas cannot exist below the gate electrode even when no recess is formed on a portion immediately beneath the gate electrode on the barrier layer, so that the enhancement operation becomes possible.Type: ApplicationFiled: June 21, 2004Publication date: March 17, 2005Applicant: FUJITSU LIMITEDInventors: Yoshimi Yamashita, Akira Endoh, Keiji Ikeda
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Publication number: 20030209715Abstract: A first film of rare-earth metal is formed on a semiconductor region of compound semiconductor exposed on a substrate. A second film essentially comprising silicon is formed on the surface of the first film. The first and second films are heated to silicidate at least a portion of the first film in contact with the second film. It is possible to lower the contact resistance of an ohmic electrode formed on semiconductor having a wide band gap.Type: ApplicationFiled: May 6, 2003Publication date: November 13, 2003Applicant: FUJITSU LIMITEDInventors: Keiji Ikeda, Yoshimi Yamashita
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Patent number: 6351410Abstract: A ferromagnetic tunnel junction random access memory includes a ferromagnetic tunnel junction structure including a first ferromagnetic layer, a second ferromagnetic layer disposed adjacent to the first ferromagnetic layer and having a fixed magnetization, and a tunnel insulator layer interposed between the first and second ferromagnetic layers; a conductor plug penetrating the first ferromagnetic layer, the tunnel insulator layer and the second ferromagnetic layer along a center axis; a first selection line coupled to a first end of the conductor plug; and a second selection line coupled to a second end of the conductor plug opposite to the first end. The first ferromagnetic layer has a generally ring shape surrounding the conductor plug and is insulated from the conductor plug. One of the first and second ferromagnetic layers has an antiferromagnetic layer pattern on a portion thereof.Type: GrantFiled: September 13, 2000Date of Patent: February 26, 2002Assignee: Fujitsu LimitedInventors: Hiroshi Nakao, Yoshimi Yamashita, Naoto Horiguchi
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Patent number: 5276724Abstract: Several ten thousands or several millions of juxtaposed hollow thin tubes, each having a diameter of, for example, 12 .mu.m and a length of 1 mm, are joined to each other to form a window having a predetermined open surface area. The window having a diameter of, for example, 30 mm, can withstand a differential pressure of several atm. A high-vacuum X-ray source and the window consisting of thin tubes having the aforementioned dimensions are connected through a differential evacuating device having a plurality of stages connected with a partitioning wall having an orifice of predetermined dimensions provided between the adjacent stages. The pressures at the two sides of the window are maintained to the atmospheric pressure and a pressure which is 1/10th of the atmospheric pressure, respectively. X-rays having a long wavelength of 10 .ANG.Type: GrantFiled: September 15, 1992Date of Patent: January 4, 1994Assignee: Fujitsu LimitedInventors: Fumiaki Kumasaka, Yoshimi Yamashita, Kei Horiuchi, Yasuo Nara
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Patent number: 4996700Abstract: Irradiation equipment comprising a beam duct disposed along the synchrotron radiation beam, and a multistage axial flow turbine installed in the beam duct. The multistage axial flow turbine comprises a plurality of stators and rotors arranged alternately in an axial direction. Each stator has vanes and a beam transmission hole formed through the vane region. Each rotor has vanes and gaps between adjacent vanes. A plurality of beam transmission holes are aligned in a direction of the synchrotron radiation beam, and a plurality of gaps of the rotors are intermittently aligned in the direction of the synchrotron radiation beam, whereby the synchrotron radiation beam can intermittently penetrate through the multistage axial flow turbine through the beam transmission holes and gaps with rotation of the rotor.Type: GrantFiled: November 27, 1989Date of Patent: February 26, 1991Assignee: Fujitsu LimitedInventors: Yoshimi Yamashita, Kei Horiuchi
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Patent number: 4849368Abstract: Disclosed is a method of producing a compound semiconductor device comprising an enhancement-mode transistor and a depletion-mode transistor, each of which has a heterojunction and utilizes a two-dimensional electron gas. The method of producing the device comprises the steps of: forming an undoped GaAs channel layer on a semi-insulating GaAs substrate; forming an N-type AlGaAs electron-supply layer so as to form the heterojunction; forming an N-type GaAs layer; forming an AlGaAs layer; selectively etching the AlGaAs layer to form a recess; performing an etching treatment using an etchant which can etch rapidly GaAs and etch slowly AlGaAs to form simultaneously grooves for gate electrodes of the enhancement-mode transistor and the depletion-mode transistor, the bottoms of the grooves being in the N-type AlGaAs layer and the distance between the bottoms being equal to the thickness of the AlGaAs layer; and forming simultaneously the gate electrodes in the grooves.Type: GrantFiled: January 21, 1988Date of Patent: July 18, 1989Assignee: Fujitsu LimitedInventors: Yoshimi Yamashita, Kinjiro Kosemura, Hidetoshi Ishiwari, Sumio Yamamoto, Shigeru Kuroda
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Patent number: 4742379Abstract: A compound semiconductor device comprises an enhancement-mode transistor and a depletion-mode transistor, each of which has a heterojunction and utilizes a two-dimensional electron gas. The method of producing the device comprises the steps of: forming an undoped GaAs channel layer on a semi-insulating GaAs substrate; forming an N-type AlGaAs electron-supply layer so as to form the heterojunction; forming an N-type GaAs layer; forming an AlGaAs layer; selectively etching the AlGaAs layer to form a recess; performing an etching treatment using an etchant which can etch rapidly GaAs and etch slowly AlGaAs to form simultaneously grooves for gate electrodes of the enhancement-mode transistor and the depletion-mode transistor, the bottoms of the grooves being in the N-type AlGaAs layer and the distance between the bottoms being equal to the thickness of the AlGaAs layer; and forming simultaneously the gate electrodes in the grooves.Type: GrantFiled: November 29, 1984Date of Patent: May 3, 1988Assignee: Fujitsu LimitedInventors: Yoshimi Yamashita, Kinjiro Kosemura, Hidetoshi Ishiwari, Sumio Yamamoto, Shigeru Kuroda