Patents by Inventor Yoshimitsu Itoh

Yoshimitsu Itoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240337026
    Abstract: An ultra-thin film of a thermosetting resin, such as a phenolic resin, can be produced by a method that includes introducing a solution containing an aldehyde-based compound and a compound (A) capable of undergoing addition condensation with an aldehyde-based compound into an electrochemical cell, which includes a working electrode and a counter electrode, and applying a positive potential to the working electrode to form a thin film on the working electrode.
    Type: Application
    Filed: May 27, 2021
    Publication date: October 10, 2024
    Inventors: Takuzo AIDA, Yoshimitsu ITOH, Tengfei FU, Pier-Luc CHAMPAGNE, Tsutomu SUZUKI, Atsuteka NAGAO
  • Patent number: 6762460
    Abstract: A protection circuit including a power supply terminal supplied with a power supply potential, a reference terminal supplied with a reference potential, and a first p-channel MOS transistor having a first gate, a first source, a first drain and a first back gate. The first gate, the first source and the first back gate are connected to the power supply terminal. Also included is a second p-channel MOS transistor having a second gate, a second source, a second drain and the first back gate, in which the second source of the second p-channel MOS transistor is connected to the first drain of the first p-channel MOS transistor, and the second gate and the second drain of the second p-channel MOS transistor is connected to the reference terminal.
    Type: Grant
    Filed: October 23, 2001
    Date of Patent: July 13, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Takiba, Masanori Kinugasa, Yoshimitsu Itoh, Masaru Mizuta
  • Publication number: 20020053697
    Abstract: A power supply terminal is supplied with a power supply potential. A reference terminal is supplied with a reference potential. First and second p-channel MOS transistor, and first and second n-channel MOS transistor each has a gate, a source, a drain, and a back gate. The gate, source and back gate of the first pMOS transistor, the back gate of the second pMOS transistor, and the gate and drain of the second nMOS transistor are connected to the power supply terminal. The source of the second pMOS transistor is connected to the drain of the first pMOS transistor. The gate and drain of the second pMOS transistor, the gate, source and back gate of the first nMOS transistor, and the back gate of the second nMOS transistor are connected to the reference terminal. The source of the second nMOS transistor is connected to the drain of the first nMOS transistor.
    Type: Application
    Filed: October 23, 2001
    Publication date: May 9, 2002
    Inventors: Akira Takiba, Masanori Kinugasa, Yoshimitsu Itoh, Masaru Mizuta
  • Patent number: 6337603
    Abstract: A temperature detector circuit for converting a forward drop voltage of a diode to digital data by means of an AD converter is provided. In order to restrict an occurrence of an output error caused by dispersion in diode manufacture, correction data according to digital data obtained by the AD converter is stored in advance in a storage circuit under a known arbitrary temperature condition, and subtraction is performed between digital data obtained by the AD converter under an unknown temperature condition and correction data read from a storage circuit, thereby to perform correction.
    Type: Grant
    Filed: June 29, 2000
    Date of Patent: January 8, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masanori Kinugasa, Yoshimitsu Itoh, Masaru Mizuta, Akira Takiba, Shinji Inada