Abstract: A method for manufacturing a junction semiconductor device having a drain region including a low-resistance layer of a first conductive type formed on one surface of a semiconductor crystal, a source region including a low-resistance layer of a first conductive type formed on the other surface of the semiconductor crystal, a gate region of a second conductive type formed on the periphery of the source region, a high-resistance layer of a first conductive type between the source region and the drain region, and a recombination-inhibiting semiconductor layer of a second conductive type provided in the vicinity of the surface of the semiconductor crystal between the gate region and the source region.

Abstract: A power semiconductor module having an integral circuit board with a metal substrate electrode, an insulation substrate and a heat sink joined is disclosed. A SiC semiconductor power device is joined to a top of the metal substrate electrode of the circuit board. A difference in average coefficients of thermal expansion between constituent materials of the circuit board in a temperature range from room to joining time temperatures is 2.0 ppm/° C. or less, and a difference in expansion, produced by a difference between a lowest operating temperature and a joining temperature, of the circuit-board constituent materials is 2,000 ppm or less.

Abstract: A method for manufacturing a junction semiconductor device, having a step for forming a first high-resistance layer, a step for forming a channel-doped layer, a step for forming a second high-resistance layer, a step for forming a low-resistance layer of a first conductive type that acts as a source region, a step for performing partial etching to a midway depth of the second high-resistance layer and the low-resistance layer, a step for forming a gate region below the portion etched in the etching step, and a step for forming a protective film on the surface of the region between the gate region and the source region. A gate region is formed using relatively low energy ion implantation in the surface that has been etched in advance to a height that is between the lower surface of the source area and the upper surface of the channel-doped layer.

Abstract: A method for manufacturing a junction semiconductor device having a drain region including a low-resistance layer of a first conductive type formed on one surface of a semiconductor crystal, a source region including a low-resistance layer of a first conductive type formed on the other surface of the semiconductor crystal, a gate region of a second conductive type formed on the periphery of the source region, a high-resistance layer of a first conductive type between the source region and the drain region, and a recombination-inhibiting semiconductor layer of a second conductive type provided in the vicinity of the surface of the semiconductor crystal between the gate region and the source region.

Abstract: A junction semiconductor device having a drain region including a low-resistance layer of a first conductive type formed on one surface of a semiconductor crystal, a source region including a low-resistance layer of a first conductive type formed on the other surface of the semiconductor crystal, a gate region of a second conductive type formed on the periphery of the source region, a high-resistance layer of a first conductive type between the source region and the drain region, and a recombination-inhibiting semiconductor layer of a second conductive type provided in the vicinity of the surface of the semiconductor crystal between the gate region and the source region.

Abstract: A power semiconductor module having an integral circuit board with a metal substrate electrode, an insulation substrate and a heat sink joined is disclosed. A SiC semiconductor power device is joined to a top of the metal substrate electrode of the circuit board. A difference in average coefficients of thermal expansion between constituent materials of the circuit board in a temperature range from room to joining time temperatures is 2.0 ppm/° C. or less, and a difference in expansion, produced by a difference between a lowest operating temperature and a joining temperature, of the circuit-board constituent materials is 2,000 ppm or less.

Abstract: A method for manufacturing a junction semiconductor device, having a step for forming a first high-resistance layer, a step for forming a channel-doped layer, a step for forming a second high-resistance layer, a step for forming a low-resistance layer of a first conductive type that acts as a source region, a step for performing partial etching to a midway depth of the second high-resistance layer and the low-resistance layer, a step for forming a gate region below the portion etched in the etching step, and a step for forming a protective film on the surface of the region between the gate region and the source region. A gate region is formed using relatively low energy ion implantation in the surface that has been etched in advance to a height that is between the lower surface of the source area and the upper surface of the channel-doped layer.

Abstract: A junction semiconductor device having a drain region comprising a low-resistance layer of a first conductive type formed on one surface of a semiconductor crystal, a source region comprising a low-resistance layer of a first conductive type formed on the other surface of the semiconductor crystal, a gate region of a second conductive type formed on the periphery of the source region, a high-resistance layer of a first conductive type between the source region and the drain region, and a recombination-inhibiting semiconductor layer of a second conductive type provided in the vicinity of the surface of the semiconductor crystal between the gate region and the source region.

Abstract: The present invention provide a solar cell and a method of manufacturing the same which is high in the efficiency of energy conversion and improved in the durability while its production process requires not particularly high accuracy.

Abstract: A semiconductor substrate has a surface layer disposed underneath a gate electrode of a field-effect transistor and having a resistance higher than the resistance of an inner layer which is formed in the semiconductor substrate below the surface layer. The surface layer is formed when a donor doped in the surface layer and an acceptor generated based on a compressive stress which is developed in the surface layer when the gate electrode is formed substantially cancel out each other. The field-effect transistor operates alternatively as a junction field-effect transistor when the surface layer is turned into a p-type structure when a compressive stress is generated in the surface layer and a metal semiconductor field-effect transistor when the surface layer is turned into an n-type structure when a tensile stress is generated in the surface layer.

Abstract: Paper having a relatively high rigidity including Japanese paper and fibrous sheet such as vegetable fibrous sheet and nonwoven fabric are used as base materials for finishing without subjected to any processing while fibrous sheets including some sorts of Japanese paper and spunbonded nonwoven fabric being high in softness and flexibility and bulky, and machine-made paper being lightweight and thin, and moreover having a relatively high rigidity are incapable of or nondurable to physical processing such as beating, bending and crumpling, so that the pretreatment or preliminary processing (primary processing) is applied to these sheets for use as base materials in such a manner that they are resin-treated or have plastic material, elastomer film, woven cloth or one selected from a group of fibrous sheets similar to the above attached thereto so as to convert them into composite sheets.

Abstract: A wafer comprising a GaAs substrate and an AlGaAs layer deposited thereon is rotated in a spin etching process. To the GaAs substrate of the rotating wafer, there is supplied an ammoniacal etching solution for selectively etching the GaAs substrate to form a groove therein. The ammoniacal etching solution comprises a mixture of hydrogen peroxide and aqueous ammonia, the volume ratio of hydrogen peroxide and aqueous ammonia being in the range from about 20 to 60. While the GaAs substrate is being selectively etched by the ammoniacal solution, the rotational speed of the wafer is progressively increased stepwise or continuously. The etching solution whose volume ratio of hydrogen peroxide and aqueous ammonia is in the range from about 20 to 60 is suitable for the formation of a deep groove in the GaAs substrate.