Patents by Inventor Yoshimitsu Shimojo

Yoshimitsu Shimojo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11994438
    Abstract: A communication device of an embodiment includes a normal operation mode and a low-power consumption mode and includes a first memory unit, a second memory unit, and a control unit. The first memory unit includes a work area for execution of firmware configured to perform basic control of the communication device. The second memory unit stores software for communication with an external device. When transition is performed from the normal operation mode to the low-power consumption mode, the control unit stops voltage supply to the first memory unit and performs control to reduce voltage supplied to the second memory unit to lower than a voltage in the normal operation mode.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: May 28, 2024
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Yoshimitsu Shimojo, Kiichiro Oya
  • Publication number: 20230299782
    Abstract: An integrated circuit of an embodiment includes a plurality of AD conversion circuits including a first AD conversion circuit and a second AD conversion circuit, and a control circuit configured to delay a start time of sampling processing of the second AD conversion circuit as compared with a usual start time such that the first AD conversion circuit is not influenced by noise generated by the sampling processing of the second AD conversion circuit, and to shorten a sampling time period to control a termination time of the sampling processing of the second AD conversion circuit to be concurrent with a termination time in a case of performing usual sampling processing.
    Type: Application
    Filed: August 22, 2022
    Publication date: September 21, 2023
    Inventor: Yoshimitsu SHIMOJO
  • Publication number: 20220074804
    Abstract: A communication device of an embodiment includes a normal operation mode and a low-power consumption mode and includes a first memory unit, a second memory unit, and a control unit. The first memory unit includes a work area for execution of firmware configured to perform basic control of the communication device. The second memory unit stores software for communication with an external device. When transition is performed from the normal operation mode to the low-power consumption mode, the control unit stops voltage supply to the first memory unit and performs control to reduce voltage supplied to the second memory unit to lower than a voltage in the normal operation mode.
    Type: Application
    Filed: February 17, 2021
    Publication date: March 10, 2022
    Inventors: Yoshimitsu Shimojo, Kiichiro Oya
  • Patent number: 9826538
    Abstract: A semiconductor integrated circuit for a radio communication terminal sequentially uses a plurality of frequency channels by instructions from a hopping frequency decision unit to receive packet data by a reception unit. When the integrated circuit cannot detect the head of the packet data in reception operations, the integrated circuit cannot receive packet data should be received originally then assumes that the received packet data is a packet error. And the integrated circuit calculates packet error rates for each frequency channel on the basis of the number of times of reception operations performed for each frequency channel and of the number of times of packet errors to estimate channel qualities by using the packet error rates.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: November 21, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Toshiki Kizu, Yoshimitsu Shimojo, Yoshinori Shigeta, Yasuro Shobatake
  • Publication number: 20160021675
    Abstract: A semiconductor integrated circuit for a radio communication terminal sequentially uses a plurality of frequency channels by instructions from a hopping frequency decision unit to receive packet data by a reception unit. When the integrated circuit cannot detect the head of the packet data in reception operations, the integrated circuit cannot receive packet data should be received originally then assumes that the received packet data is a packet error. And the integrated circuit calculates packet error rates for each frequency channel on the basis of the number of times of reception operations performed for each frequency channel and of the number of times of packet errors to estimate channel qualities by using the packet error rates.
    Type: Application
    Filed: September 29, 2015
    Publication date: January 21, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Toshiki KIZU, Yoshimitsu Shimojo, Yoshinori Shigeta, Yasuro Shobatake
  • Patent number: 9178687
    Abstract: A semiconductor integrated circuit for a radio communication terminal sequentially uses a plurality of frequency channels by instructions from a hopping frequency decision unit to receive packet data by a reception unit. When the integrated circuit cannot detect the head of the packet data in reception operations, the integrated circuit cannot receive packet data should be received originally then assumes that the received packet data is a packet error. And the integrated circuit calculates packet error rates for each frequency channel on the basis of the number of times of reception operations performed for each frequency channel and of the number of times of packet errors to estimate channel qualities by using the packet error rates.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: November 3, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Toshiki Kizu, Yoshimitsu Shimojo, Yoshinori Shigeta, Yasuro Shobatake
  • Publication number: 20140328376
    Abstract: A semiconductor integrated circuit for a radio communication terminal sequentially uses a plurality of frequency channels by instructions from a hopping frequency decision unit to receive packet data by a reception unit. When the integrated circuit cannot detect the head of the packet data in reception operations, the integrated circuit cannot receive packet data should be received originally then assumes that the received packet data is a packet error. And the integrated circuit calculates packet error rates for each frequency channel on the basis of the number of times of reception operations performed for each frequency channel and of the number of times of packet errors to estimate channel qualities by using the packet error rates.
    Type: Application
    Filed: July 15, 2014
    Publication date: November 6, 2014
    Inventors: Toshiki KIZU, Yoshimitsu Shimojo, Yoshinori Shigeta, Yasuro Shobatake
  • Patent number: 8804788
    Abstract: A semiconductor integrated circuit for a radio communication terminal sequentially uses a plurality of frequency channels by instructions from a hopping frequency decision unit to receive packet data by a reception unit. When the integrated circuit cannot detect the head of the packet data in reception operations, the integrated circuit cannot receive packet data should be received originally then assumes that the received packet data is a packet error. And the integrated circuit calculates packet error rates for each frequency channel on the basis of the number of times of reception operations performed for each frequency channel and of the number of times of packet errors to estimate channel qualities by using the packet error rates.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: August 12, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiki Kizu, Yoshimitsu Shimojo, Yoshinori Shigeta, Yasuro Shobatake
  • Patent number: 8792533
    Abstract: A semiconductor integrated circuit for a radio communication terminal sequentially uses a plurality of frequency channels by instructions from a hopping frequency decision unit to receive packet data by a reception unit. When the integrated circuit cannot detect the head of the packet data in reception operations, the integrated circuit cannot receive packet data should be received originally then assumes that the received packet data is a packet error. And the integrated circuit calculates packet error rates for each frequency channel on the basis of the number of times of reception operations performed for each frequency channel and of the number of times of packet errors to estimate channel qualities by using the packet error rates.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: July 29, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiki Kizu, Yoshimitsu Shimojo, Yoshinori Shigeta, Yasuro Shobatake
  • Patent number: 8406273
    Abstract: A semiconductor integrated circuit for a radio communication terminal sequentially uses a plurality of frequency channels by instructions from a hopping frequency decision unit to receive packet data by a reception unit. When the integrated circuit cannot detect the head of the packet data in reception operations, the integrated circuit cannot receive packet data should be received originally then assumes that the received packet data is a packet error. And the integrated circuit calculates packet error rates for each frequency channel on the basis of the number of times of reception operations performed for each frequency channel and of the number of times of packet errors to estimate channel qualities by using the packet error rates.
    Type: Grant
    Filed: July 10, 2009
    Date of Patent: March 26, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiki Kizu, Yoshimitsu Shimojo, Yoshinori Shigeta, Yasuro Shobatake
  • Patent number: 8190891
    Abstract: A transmitter has a network interface unit connected to a wireless network capable of transmitting contents for which copyright protection is necessary, an encryption processing unit configured to encrypt contents for which copyright protection is necessary, an RTT measuring unit configured to measure a round trip time after a predetermined packet is transmitted to a receiver, until a response corresponding to the transmitted packet is received, a communication permission determination unit configured to permit transmission of the contents for which copyright protection is necessary when the round trip time measured by the RTT measuring unit is within a predetermined time, and a parameter modification unit configured to change parameters of the wireless network before and/or after the RTT measuring unit performs the measurement of the round trip time.
    Type: Grant
    Filed: September 6, 2006
    Date of Patent: May 29, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Saito, Yoshimitsu Shimojo
  • Patent number: 7808950
    Abstract: A radio communication apparatus determines whether a reception signal is received normally. The apparatus measures strengths of the reception signal, assesses frequency channels using a result whether the reception signal is received normally and a strength of the reception signal, and decides that zero or more of the frequency channels as unusable channel in accordance with a result of an assessment of the frequency channels. The apparatus transmits a radio signal using one of the frequency channels sequentially without using the unusable channel.
    Type: Grant
    Filed: October 25, 2005
    Date of Patent: October 5, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiki Kizu, Yoshimitsu Shimojo
  • Publication number: 20090274193
    Abstract: A semiconductor integrated circuit for a radio communication terminal sequentially uses a plurality of frequency channels by instructions from a hopping frequency decision unit to receive packet data by a reception unit. When the integrated circuit cannot detect the head of the packet data in reception operations, the integrated circuit cannot receive packet data should be received originally then assumes that the received packet data is a packet error. And the integrated circuit calculates packet error rates for each frequency channel on the basis of the number of times of reception operations performed for each frequency channel and of the number of times of packet errors to estimate channel qualities by using the packet error rates.
    Type: Application
    Filed: July 10, 2009
    Publication date: November 5, 2009
    Inventors: Toshiki Kizu, Yoshimitsu Shimojo, Yoshinori Shigeta, Yasuro Shobatake
  • Patent number: 7480247
    Abstract: A packet switch and a packet switching method capable of taking the full advantage of the transfer capability of the packet switch by avoiding the influence due to the congestion are disclosed. In the packet switch, the priority level according to the congestion states of the transfer target is attached to a packet, and the processing at a time of packet collision is carried out by accounting for this priority level, so that it becomes possible to carry out the packet transfer control according to the congestion status of the transfer target of each packet.
    Type: Grant
    Filed: September 23, 2003
    Date of Patent: January 20, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshimitsu Shimojo, Hideaki Nakakita
  • Publication number: 20080192935
    Abstract: A transmitter has a network interface unit connected to a wireless network capable of transmitting contents for which copyright protection is necessary, an encryption processing unit configured to encrypt contents for which copyright protection is necessary, an RTT measuring unit configured to measure a round trip time after a predetermined packet is transmitted to a receiver, until a response corresponding to the transmitted packet is received, a communication permission determination unit configured to permit transmission of the contents for which copyright protection is necessary when the round trip time measured by the RTT measuring unit is within a predetermined time, and a parameter modification unit configured to change parameters of the wireless network before and/or after the RTT measuring unit performs the measurement of the round trip time.
    Type: Application
    Filed: September 6, 2006
    Publication date: August 14, 2008
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Saito, Yoshimitsu Shimojo
  • Publication number: 20060188004
    Abstract: A semiconductor integrated circuit for a radio communication terminal sequentially uses a plurality of frequency channels by instructions from a hopping frequency decision unit to receive packet data by a reception unit. When the integrated circuit cannot detect the head of the packet data in reception operations, the integrated circuit cannot receive packet data should be received originally then assumes that the received packet data is a packet error. And the integrated circuit calculates packet error rates for each frequency channel on the basis of the number of times of reception operations performed for each frequency channel and of the number of times of packet errors to estimate channel qualities by using the packet error rates.
    Type: Application
    Filed: January 27, 2006
    Publication date: August 24, 2006
    Inventors: Toshiki Kizu, Yoshimitsu Shimojo, Yoshinori Shigeta, Yasuro Shobatake
  • Publication number: 20060089149
    Abstract: A radio communication apparatus determines whether a reception signal is received normally. The apparatus measures strengths of the reception signal, assesses frequency channels using a result whether the reception signal is received normally and a strength of the reception signal, and decides that zero or more of the frequency channels as unusable channel in accordance with a result of an assessment of the frequency channels. The apparatus transmits a radio signal using one of the frequency channels sequentially without using the unusable channel.
    Type: Application
    Filed: October 25, 2005
    Publication date: April 27, 2006
    Inventors: Toshiki Kizu, Yoshimitsu Shimojo
  • Patent number: 7027442
    Abstract: A packet processing device is formed by a digest information generation unit configured to extract a plurality of prescribed bit sequences from an input packet, and generate a digest information capable of specifying at least a part of a processing to be applied to the input packet, according to values of the plurality of prescribed bit sequences; and a packet processing unit configured to process the input packet using an instruction sequence to be applied to the input packet that is obtained according to the digest information generated by the digest information generation unit, where the digest information generation unit generates the digest information with respect to a next input packet while the packet processing unit carries out a processing for one packet.
    Type: Grant
    Filed: September 7, 2004
    Date of Patent: April 11, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenji Shirakawa, Yasuro Shobatake, Toshio Okamoto, Yoshimitsu Shimojo
  • Patent number: 6999419
    Abstract: A communication resource management scheme capable of guaranteeing the communication quality with respect to the flow while not requiring the processing for each flow to nodes other than edge nodes is disclosed. The edge node stores an information for obtaining an available amount of communication resources that can be newly allocated in the network to one set of flows which share at least a route from that edge node to an egress node of the network.
    Type: Grant
    Filed: October 14, 2003
    Date of Patent: February 14, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kataro Ise, Yoshimitsu Shimojo, Yasuhiro Katsube
  • Patent number: 6934296
    Abstract: A packet transfer device that can be easily realized even when a number of input ports is large. Each input buffer temporarily stores entered packets class by class, and outputs packets of a selected class specified by the control unit, while the control unit determines the selected class of packets to be outputted from the input buffers according to a packet storage state in the packet storage units of the input buffers as a whole for each class. Each input buffer can temporarily store entered packets while selecting packets to be outputted at a next phase, and the control unit can specify packets to be selected in the input buffers according to an output state of packets previously selected in the input buffers as a whole. Packets stored in the buffer can be managed in terms of a plurality of groups, and each packet entered at the buffer can be distributed into a plurality of groups so that packets are distributed fairly among flows.
    Type: Grant
    Filed: July 9, 2002
    Date of Patent: August 23, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshimitsu Shimojo