Patents by Inventor Yoshimitsu TAKENOUCHI

Yoshimitsu TAKENOUCHI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11769702
    Abstract: An amplifier IC mounted on a multilayer board includes input, output, and common terminals. The multilayer board includes common, input, and output terminals on board side. These terminals are connected to the corresponding terminals on device side via bumps. On the lower surface of the multilayer board, a lower surface common terminal is arranged at a location overlapping the common terminal in plan view. First, second, and third via conductors are sequentially arranged toward the lower surface common terminal from the common terminal. An input via conductor is connected to the input terminal on board side. In plan view, the area of the first common via conductor is larger than any one of the areas of the second and third common via conductors and the input via conductor. In plan view, the area of bump of the common terminal is larger than the area of bump of the input terminal.
    Type: Grant
    Filed: April 7, 2021
    Date of Patent: September 26, 2023
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Shigeki Koya, Yoshimitsu Takenouchi, Kenji Sasaki, Masao Kondo
  • Publication number: 20210327775
    Abstract: An amplifier IC mounted on a multilayer board includes input, output, and common terminals. The multilayer board includes common, input, and output terminals on board side. These terminals are connected to the corresponding terminals on device side via bumps. On the lower surface of the multilayer board, a lower surface common terminal is arranged at a location overlapping the common terminal in plan view. First, second, and third via conductors are sequentially arranged toward the lower surface common terminal from the common terminal. An input via conductor is connected to the input terminal on board side. In plan view, the area of the first common via conductor is larger than any one of the areas of the second and third common via conductors and the input via conductor. In plan view, the area of bump of the common terminal is larger than the area of bump of the input terminal.
    Type: Application
    Filed: April 7, 2021
    Publication date: October 21, 2021
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Shigeki KOYA, Yoshimitsu TAKENOUCHI, Kenji SASAKI, Masao KONDO