Abstract: An integrated circuit semiconductor device includes a nanosheet extending above a substrate in a first horizontal direction, a gate electrode extending in a second horizontal direction while surrounding the nanosheet with a gate insulating layer therebetween, a first source/drain region on a side of the nanosheet, and a second source/drain region on another side of the nanosheet, wherein the first source/drain region includes first silicide layers provided inward from surfaces of the nanosheet, first metal layers surrounding the nanosheet from upper and lower sides of the first silicide layers, and a first nanosheet region provided between the first silicide layers, wherein the second source/drain region includes second silicide layers formed inward from the surfaces of the nanosheet, second metal layers surrounding the nanosheet from upper and lower sides of the second silicide layers, and a second nanosheet region provided between the second silicide layers.

Abstract: A semiconductor device comprises a substrate, a first active pattern on the substrate and extending in a first direction, a second active pattern extending in the first direction spaced apart from the substrate, a gate electrode extending in a second direction surrounding the first and second active patterns, and a high dielectric film between the first and second active patterns and the gate electrode. The gate electrode includes first and second work function adjusting films surrounding the high dielectric film on the first and second active patterns, and a filling conductive film surrounding the first and second work function adjusting films. The first and second work function adjusting films include first and second work function conductive films, each of which includes a first metal film. A thickness of the first metal film of the first work function conductive film is greater than that of the second work function conductive film.

Abstract: A semiconductor device includes first to fourth cells sequentially disposed on a substrate, first to third diffusion break structures, a first fin structure configured to protrude from the substrate, the first fin structure comprising first to fourth fins separated from each other by the first to third diffusion break structures, a second fin structure configured to protrude from the substrate, to be spaced apart from the first fin structure, the second fin structure comprising fifth to eighth fins separated from each other by the first to third diffusion break structures, the first to fourth gate electrodes being disposed in the first to fourth cells, respectively, and the number of fins in one cell of the first to fourth cells is different from the number of fins in an other cell of the first to fourth cells.

Abstract: A semiconductor device includes first to fourth cells sequentially disposed on a substrate, first to third diffusion break structures, a first fin structure configured to protrude from the substrate, the first fin structure comprising first to fourth fins separated from each other by the first to third diffusion break structures, a second fin structure configured to protrude from the substrate, to be spaced apart from the first fin structure, the second fin structure comprising fifth to eighth fins separated from each other by the first to third diffusion break structures, the first to fourth gate electrodes being disposed in the first to fourth cells, respectively, and the number of fins in one cell of the first to fourth cells is different from the number of fins in an other cell of the first to fourth cells.

Abstract: In a method of manufacturing a semiconductor device, a plasma annealing and supplying a threshold voltage control gas onto a portion of a substrate is performed to form a fixed charge region including a fixed charge at a surface of the substrate. A MOS transistor is formed on the substrate including the fixed charge region. By the above processes, the threshold voltage of the MOS transistor may be easily controlled.

Abstract: In a method of manufacturing a semiconductor device, a plasma annealing and supplying a threshold voltage control gas onto a portion of a substrate is performed to form a fixed charge region including a fixed charge at a surface of the substrate. A MOS transistor is formed on the substrate including the fixed charge region. By the above processes, the threshold voltage of the MOS transistor may be easily controlled.

Abstract: Provided is a semiconductor device, which includes a first fin on a substrate, a first gate insulating layer including a first trench disposed on the first fin, a first work function adjusting layer in the first trench, a first barrier layer covering a top surface of the first work function adjusting layer; and an interlayer insulating layer on the first barrier layer.

Abstract: A semiconductor device includes: an active region located in an upper portion of a semiconductor substrate; a through-hole electrode penetrating the substrate, and made of a conductor having a thermal expansion coefficient larger than that of a material for the substrate; and a stress buffer region located in the upper portion of the substrate and sandwiched between the through-hole electrode and the active region. The stress buffer region does not penetrate the substrate and includes a stress buffer part made of a material having a thermal expansion coefficient larger than that of the material for the substrate and an untreated region where the stress buffer part is not present. The stress buffer part is located in at least two locations sandwiching the untreated region in a cross section perpendicular to a surface of the substrate and passing through the through-hole electrode and the active region.

Abstract: A semiconductor device includes a first transistor formed on a semiconductor substrate, and including a first channel region, and a first gate electrode formed on the first channel region, and a second transistor formed on the semiconductor substrate, and including a second channel region having a conductivity type identical to a conductivity type of the first channel region, and a second gate electrode formed on the second channel region and having a potential identical to a potential of the first gate electrode. A drain of the first transistor is electrically connected to a source of the second transistor. An absolute value of a threshold voltage of the first transistor is greater than an absolute value of a threshold voltage of the second transistor.

Abstract: In a method for manufacturing a semiconductor device having an N-channel field effect transistor, the N-channel field effect transistor is formed by a process including the steps of forming a high dielectric constant gate insulating film on a substrate, forming a gate electrode on the high dielectric constant gate insulating film, forming an extension region by introducing N-type impurities into the substrate by using at least the gate electrode as a mask, and forming a pocket region by introducing P-type impurities under the extension region in the substrate by using at least the gate electrode as a mask. An amount of arsenic (As) that is introduced as the N-type impurities is in a range that is equal to or lower than a prescribed value that is determined based on a thickness of the high dielectric constant gate insulating film.

Abstract: An embodiment of the present invention relates to a salty taste enhancer containing an amino acid and/or a derivative thereof, the amino acid being L-leucine, or L-leucine and L-isoleucine. At least one embodiment provides: (i) a salty taste enhancer which is capable of effectively enhancing a salty taste of food or drink, (ii) food or drink containing the salty taste enhancer, and/or (iii) a method for producing the food or drink.

Abstract: In a method for manufacturing a semiconductor device having an N-channel field effect transistor, the N-channel field effect transistor is formed by a process including the steps of forming a high dielectric constant gate insulating film on a substrate, forming a gate electrode on the high dielectric constant gate insulating film, forming an extension region by introducing N-type impurities into the substrate by using at least the gate electrode as a mask, and forming a pocket region by introducing P-type impurities under the extension region in the substrate by using at least the gate electrode as a mask. An amount of arsenic (As) that is introduced as the N-type impurities is in a range that is equal to or lower than a prescribed value that is determined based on a thickness of the high dielectric constant gate insulating film.

Abstract: In a method for manufacturing a semiconductor device having an N-channel field effect transistor, the N-channel field effect transistor is formed by a process including the steps of forming a high dielectric constant gate insulating film on a substrate, forming a gate electrode on the high dielectric constant gate insulating film, forming an extension region by introducing N-type impurities into the substrate by using at least the gate electrode as a mask, and forming a pocket region by introducing P-type impurities under the extension region in the substrate by using at least the gate electrode as a mask. An amount of arsenic (As) that is introduced as the N-type impurities is in a range that is equal to or lower than a prescribed value that is determined based on a thickness of the high dielectric constant gate insulating film.

Abstract: A gate electrode is formed on a substrate via a gate insulating film. The gate insulating film includes a high dielectric constant film containing a metal, oxygen and hydrogen, and a lower barrier film formed below the high dielectric constant film and containing a metal, oxygen, silicon and nitrogen.

Abstract: In a method for manufacturing a semiconductor device having an N-channel field effect transistor, the N-channel field effect transistor is formed by a process including the steps of forming a high dielectric constant gate insulating film on a substrate, forming a gate electrode on the high dielectric constant gate insulating film, forming an extension region by introducing N-type impurities into the substrate by using at least the gate electrode as a mask, and forming a pocket region by introducing P-type impurities under the extension region in the substrate by using at least the gate electrode as a mask. An amount of arsenic (As) that is introduced as the N-type impurities is in a range that is equal to or lower than a prescribed value that is determined based on a thickness of the high dielectric constant gate insulating film.

Abstract: With keeping an atmosphere including oxygen within a chamber and with a wafer kept at a low temperature, plasma generated within the chamber is biased toward the wafer, and the wafer is subjected to the plasma. A semiconductor layer exposed on the wafer is oxidized into an oxide film. Thus, an oxide film can be formed even at room temperature differently from thermal oxidation. This oxidation is applicable to recovery of an implantation protection insulating film having been etched in cleaning a photoresist film, relaxation of a step formed between polysilicon films, relaxation of a step formed within a trench and the like. Also, before removing a photoresist film used for forming a gate electrode including a metal, a contamination protection film can be formed by this oxidation with the photoresist film kept.

Abstract: A disk storage medium and a disk drive which reduce friction during landing of the head/slider is described. The minimum fly height area of the head/slider is positioned over a texture free portion of the landing zone on the disk surface landing. In a preferred embodiment, the landing zone of a magnetic disk is a laser texture zone comprising a great number of bumps and is positioned during landing adjacent an area other than the minimum fly height area of the head/slider. The area facing the minimum fly height area of a head/slider has no bumps, i.e. is a bump free zone.

Abstract: With keeping an atmosphere including oxygen within a chamber and with a wafer kept at a low temperature, plasma generated within the chamber is biased toward the wafer, and the wafer is subjected to the plasma. A semiconductor layer exposed on the wafer is oxidized into an oxide film. Thus, an oxide film can be formed even at room temperature differently from thermal oxidation. This oxidation is applicable to recovery of an implantation protection insulating film having been etched in cleaning a photoresist film, relaxation of a step formed between polysilicon films, relaxation of a step formed within a trench and the like. Also, before removing a photoresist film used for forming a gate electrode including a metal, a contamination protection film can be formed by this oxidation with the photoresist film kept.

Abstract: With keeping an atmosphere including oxygen within a chamber and with a wafer kept at a low temperature, plasma generated within the chamber is biased toward the wafer, and the wafer is subjected to the plasma. A semiconductor layer exposed on the wafer is oxidized into an oxide film. Thus, an oxide film can be formed even at room temperature differently from thermal oxidation. This oxidation is applicable to recovery of an implantation protection insulating film having been etched in cleaning a photoresist film, relaxation of a step formed between polysilicon films, relaxation of a step formed within trench and the like. Also, before removing a photoresist film used for forming a gate electrode including a metal, a contamination protection film can be formed by this oxidation with the photoresist film kept.

Abstract: A gate electrode is formed on a substrate via a gate insulating film. The gate insulating film includes a high dielectric constant film containing a metal, oxygen and hydrogen, and a lower barrier film formed below the high dielectric constant film and containing a metal, oxygen, silicon and nitrogen.