Patents by Inventor Yoshinao Nishioka

Yoshinao Nishioka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10734159
    Abstract: A multilayer ceramic capacitor includes a substantially cuboid laminated body including ceramic layers and internal electrode layers laminated, and two or more exposed regions where the plurality of internal electrode layers are exposed, and external electrodes, wherein at least one of the external electrodes is an external electrode with resistance, the internal electrode layers include a first internal electrode layer and a second internal electrode layer opposed to the first internal electrode layer in the lamination direction, and the external electrode with resistance includes a thin film electrode layer in direct contact with the internal electrode layer in the exposed region, a resistive electrode layer provided on the thin film electrode layer, and an upper electrode layer provided on the resistive electrode layer, which has a lower electrical resistivity lower than the resistive electrode layer.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: August 4, 2020
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Takashi Sawada, Yoshinao Nishioka, Kenichi Togo
  • Patent number: 10438749
    Abstract: An electronic component includes a multilayer body including dielectric layers and inner electrodes alternately laminated together, first to third outer electrodes arranged in this order in one direction on a first main surface of the multilayer body, and fourth to sixth outer electrodes provided on a second main surface opposite to the first main surface such that at least a portion of the fourth outer electrode, at least a portion of the fifth outer electrode, and at least a portion of the sixth outer electrode respectively face the first outer electrode, the second outer electrode, and the third outer electrode. The first, third, and fifth outer electrodes are electrically connected to one another. The second, fourth, and sixth outer electrodes are electrically connected to one another and each have a polarity different from that of the first outer electrode.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: October 8, 2019
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yoshinao Nishioka, Yasuo Fujii
  • Publication number: 20180211785
    Abstract: An electronic component includes a multilayer body including dielectric layers and inner electrodes alternately laminated together, first to third outer electrodes arranged in this order in one direction on a first main surface of the multilayer body, and fourth to sixth outer electrodes provided on a second main surface opposite to the first main surface such that at least a portion of the fourth outer electrode, at least a portion of the fifth outer electrode, and at least a portion of the sixth outer electrode respectively face the first outer electrode, the second outer electrode, and the third outer electrode. The first, third, and fifth outer electrodes are electrically connected to one another. The second, fourth, and sixth outer electrodes are electrically connected to one another and each have a polarity different from that of the first outer electrode.
    Type: Application
    Filed: January 22, 2018
    Publication date: July 26, 2018
    Inventors: Yoshinao NISHIOKA, Yasuo FUJII
  • Publication number: 20180182552
    Abstract: A multilayer ceramic capacitor includes a substantially cuboid laminated body including ceramic layers and internal electrode layers laminated, and two or more exposed regions where the plurality of internal electrode layers are exposed, and external electrodes, wherein at least one of the external electrodes is an external electrode with resistance, the internal electrode layers include a first internal electrode layer and a second internal electrode layer opposed to the first internal electrode layer in the lamination direction, and the external electrode with resistance includes a thin film electrode layer in direct contact with the internal electrode layer in the exposed region, a resistive electrode layer provided on the thin film electrode layer, and an upper electrode layer provided on the resistive electrode layer, which has a lower electrical resistivity lower than the resistive electrode layer.
    Type: Application
    Filed: December 21, 2017
    Publication date: June 28, 2018
    Inventors: Takashi SAWADA, Yoshinao NISHIOKA, Kenichi TOGO
  • Patent number: 9502178
    Abstract: A monolithic capacitor includes a laminated body including stacked dielectric layers and substantially in the shape of a rectangular parallelepiped, and including a first surface being a mounting surface, a second surface opposite to the first surface, opposing third and fourth surfaces orthogonal to the first and second surfaces, and opposing fifth and sixth surfaces orthogonal to the first to fourth surfaces; capacitor electrodes disposed in the laminated body and each including a capacitive portion and a lead portion extending therefrom to at least one surface of the laminated body, the capacitive portions facing each other with dielectric layers interposed therebetween; and first and second outer electrodes disposed on at least one surface of the laminated body and connected to the lead portions. A gap between the first surface and the capacitive portions is greater than a gap between the second surface and the capacitive portions.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: November 22, 2016
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yasuo Fujii, Yoshinao Nishioka
  • Patent number: 9491849
    Abstract: A mounting structure includes an electronic component mounted on a circuit board. Land electrodes are disposed on a board body and are connected to outer electrodes of the electronic component through solders, respectively. A distance from each of the land electrodes to a top of the corresponding solder is not larger than about 1.27 times a distance from each of the land electrodes to an exposed portion of a capacitor conductor exposed at an end surface of the electronic component, the capacitor conductor being positioned closest to the circuit board.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: November 8, 2016
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yasuo Fujii, Yoshinao Nishioka
  • Patent number: 9404732
    Abstract: An electronic component thickness measurement method includes extracting, from a plurality of second reference lines in first image data and a plurality of second reference lines in second image data, only a second reference line at which a difference in intensity peak between respective second reference lines at a same position in the first image data and the second image data is smallest, and forming third image data including a first reference line and the extracted second reference line, and calculating a thickness of the electronic component from a distance between the first reference line and the second reference line in the third image data.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: August 2, 2016
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yoshinao Nishioka, Masayoshi Haruki
  • Publication number: 20150016071
    Abstract: An electronic component thickness measurement method includes extracting, from a plurality of second reference lines in first image data and a plurality of second reference lines in second image data, only a second reference line at which a difference in intensity peak between respective second reference lines at a same position in the first image data and the second image data is smallest, and forming third image data including a first reference line and the extracted second reference line, and calculating a thickness of the electronic component from a distance between the first reference line and the second reference line in the third image data.
    Type: Application
    Filed: July 8, 2014
    Publication date: January 15, 2015
    Inventors: Yoshinao NISHIOKA, Masayoshi HARUKI
  • Publication number: 20140153155
    Abstract: A monolithic capacitor includes a laminated body including stacked dielectric layers and substantially in the shape of a rectangular parallelepiped, and including a first surface being a mounting surface, a second surface opposite to the first surface, opposing third and fourth surfaces orthogonal to the first and second surfaces, and opposing fifth and sixth surfaces orthogonal to the first to fourth surfaces; capacitor electrodes disposed in the laminated body and each including a capacitive portion and a lead portion extending therefrom to at least one surface of the laminated body, the capacitive portions facing each other with dielectric layers interposed therebetween; and first and second outer electrodes disposed on at least one surface of the laminated body and connected to the lead portions. A gap between the first surface and the capacitive portions is greater than a gap between the second surface and the capacitive portions.
    Type: Application
    Filed: June 11, 2013
    Publication date: June 5, 2014
    Inventors: Yasuo FUJII, Yoshinao NISHIOKA
  • Publication number: 20140008116
    Abstract: A mounting structure includes an electronic component mounted on a circuit board. Land electrodes are disposed on a board body and are connected to outer electrodes of the electronic component through solders, respectively. A distance from each of the land electrodes to a top of the corresponding solder is not larger than about 1.27 times a distance from each of the land electrodes to an exposed portion of a capacitor conductor exposed at an end surface of the electronic component, the capacitor conductor being positioned closest to the circuit board.
    Type: Application
    Filed: September 16, 2013
    Publication date: January 9, 2014
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Yasuo FUJII, Yoshinao NISHIOKA
  • Patent number: 8618422
    Abstract: A mounting structure includes an electronic component mounted on a circuit board. Land electrodes are disposed on a board body and are connected to outer electrodes of the electronic component through solders, respectively. A distance from each of the land electrodes to a top of the corresponding solder is not larger than about 1.27 times a distance from each of the land electrodes to an exposed portion of a capacitor conductor exposed at an end surface of the electronic component, the capacitor conductor being positioned closest to the circuit board.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: December 31, 2013
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yasuo Fujii, Yoshinao Nishioka
  • Patent number: 8581111
    Abstract: A mounting structure includes an electronic component mounted on a circuit board. Land electrodes are disposed on a board body and are connected to outer electrodes of the electronic component through solders, respectively. A distance from each of the land electrodes to a top of the corresponding solder is not larger than about 1.27 times a distance from each of the land electrodes to an exposed portion of a capacitor conductor exposed at an end surface of the electronic component, the capacitor conductor being positioned closest to the circuit board.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: November 12, 2013
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yasuo Fujii, Yoshinao Nishioka
  • Publication number: 20130233606
    Abstract: A mounting structure includes an electronic component mounted on a circuit board. Land electrodes are disposed on a board body and are connected to outer electrodes of the electronic component through solders, respectively. A distance from each of the land electrodes to a top of the corresponding solder is not larger than about 1.27 times a distance from each of the land electrodes to an exposed portion of a capacitor conductor exposed at an end surface of the electronic component, the capacitor conductor being positioned closest to the circuit board.
    Type: Application
    Filed: April 30, 2013
    Publication date: September 12, 2013
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Yasuo FUJII, Yoshinao NISHIOKA
  • Publication number: 20130056252
    Abstract: A mounting structure includes an electronic component mounted on a circuit board. Land electrodes are disposed on a board body and are connected to outer electrodes of the electronic component through solders, respectively. A distance from each of the land electrodes to a top of the corresponding solder is not larger than about 1.27 times a distance from each of the land electrodes to an exposed portion of a capacitor conductor exposed at an end surface of the electronic component, the capacitor conductor being positioned closest to the circuit board.
    Type: Application
    Filed: August 31, 2012
    Publication date: March 7, 2013
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventors: Yasuo FUJII, Yoshinao NISHIOKA
  • Patent number: 6469516
    Abstract: In a method for judging the conformity or non-conformity of a capacitor from the charging characteristic at the time when a direct-current voltage is applied to the capacitor, a threshold current value I0 of the dielectric polarization component of the capacitor is determined in advance, an evaluation function n(t) is determined based on a logarithmic value of the difference between the measured charging current value m(t) of the capacitor and the threshold current value I0 or the difference between their logarithmic values, and the evaluation function n(t) is approximated to a quadratic curve. When the quadratic coefficient of the quadratic approximation equation has a plus sign the capacitor is judged to be non-conforming, and when the coefficient has a minus sign, the capacitor is conforming.
    Type: Grant
    Filed: November 17, 1999
    Date of Patent: October 22, 2002
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yoshinao Nishioka, Mitsuru Kitagawa
  • Patent number: 6448525
    Abstract: Capacitor characteristics measurement apparatus and packing apparatus includes a turntable (1) intermittently driven at a constant pitch to supply capacitors (C) from a parts feeder (8) to a holder section (2) of the turntable (1) in a one-by-one manner. A capacitance measurement section (4) and an IR prediction section (5) are provided to determine whether each capacitor is acceptable or defective in quality based on the measured values obtainable from these sections (4, 5). The IR prediction section (5) applies a DC voltage to a capacitor while predicting the current value at termination of chargeup by use of its initial current value in the charge region of an insulation polarization component thereof upon application of the voltage thereto.
    Type: Grant
    Filed: April 7, 1998
    Date of Patent: September 10, 2002
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yoshinao Nishioka, Mitsuru Kitagawa, Masao Nishimura, Toshinari Tabata
  • Publication number: 20020060571
    Abstract: In a method for judging the conformity or non-conformity of a capacitor from the charging characteristic at the time when a direct-current voltage is applied to the capacitor, a threshold current value I0 of the dielectric polarization component of the capacitor is determined in advance, an evaluation function n(t) is determined based on a logarithmic value of the difference between the measured charging current value m(t) of the capacitor and the threshold current value I0 or the difference between their logarithmic values, and the evaluation function n(t) is approximated to a quadratic curve. When the quadratic coefficient of the quadratic approximation equation has a plus sign the capacitor is judged to be non-conforming, and when the coefficient has a minus sign, the capacitor is conforming.
    Type: Application
    Filed: November 17, 1999
    Publication date: May 23, 2002
    Inventors: YOSHINAO NISHIOKA, MITSURU KITAGAWA
  • Publication number: 20020033361
    Abstract: Capacitor characteristics measurement apparatus and packing apparatus includes a turntable (1) intermittently driven at a constant pitch to supply capacitors (C) from a parts feeder (8) to a holder section (2) of the turntable (1) in a one-by-one manner. A capacitance measurement section (4) and an IR prediction section (5) are provided to determine whether each capacitor is acceptable or defective in quality based on the measured values obtainable from these sections (4, 5). The IR prediction section (5) applies a DC voltage to a capacitor while predicting the current value at termination of chargeup by use of its initial current value in the charge region of an insulation polarization component thereof upon application of the voltage thereto.
    Type: Application
    Filed: October 17, 2001
    Publication date: March 21, 2002
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Yoshinao Nishioka, Mitsuru Kitagawa, Masao Nishimura, Toshinari Tabata
  • Patent number: 6204638
    Abstract: A capacitor can be charged at a high speed by applying a direct current voltage intermittently to the capacitor. The direct current voltage is intermittently applied to the capacitor such that a preceding applied voltage E1 is larger than a succeeding applied voltage E2. Thus, the charging is swiftly progresses and the capacitor can be charged at a higher speed than when the voltage is applied continuously.
    Type: Grant
    Filed: January 6, 1998
    Date of Patent: March 20, 2001
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yoshinao Nishioka, Toshinari Tabata
  • Patent number: 6066940
    Abstract: When DC voltages are intermittently applied to a capacitor and when an initially applied voltage E.sub.1 is higher than a subsequently applied voltage E.sub.2, charging rapidly advances even during a period in which no voltage is applied. Higher-speed charging is performed than in a case in which the same voltage is continuously applied.
    Type: Grant
    Filed: November 6, 1998
    Date of Patent: May 23, 2000
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yoshinao Nishioka, Toshinari Tabata