Abstract: A semiconductor storage device includes a first memory chip having a first memory cell, a first word line connected to the first memory cell, a first voltage step-up circuit, and a second voltage step-up circuit, and a second memory chip having a second memory cell, a second word line connected to the second memory cell, a third voltage step-up circuit, and a fourth voltage step-up circuit. During a read operation executed in the first memory chip, the first, second, and fourth voltage step-up circuits supply a first voltage to the first word line, and when a voltage of the first word line reaches a predetermined voltage, the first voltage step-up circuit continues to supply the first voltage to the first word line, and the second voltage step-up circuit and the fourth voltage step-up circuit stop supplying the first voltage to the first word line.

Abstract: A sheet feeding device includes a feeding roller pair, a detecting portion, a first changing portion, a second changing portion, and a controller for controlling the first changing portion and the second changing portion. The controller starts a first feeding operation for feeding a sheet toward the obliquely feeding roller pair in a nipping state of the feeding roller pair and then starts a second feeding operation for feeding the sheet for abutting a side end of the sheet against the reference member in the nipping state of the obliquely feeding roller pair. The controller changes, after the first feeding operation is started and before the second feeding operation is started, a start timing of the second feeding operation on the basis of a detection result of a position of the side end of the sheet detected by the detecting portion.

Abstract: A semiconductor memory device comprises a first memory cell and a second memory cell. The semiconductor memory device is configured to be able to perform: a first operation which is a read operation or the like to the first memory cell; and a second operation which is a read operation or the like to the second memory cell. The semiconductor memory device transitions to a standby mode after performing the first operation in response to an input of a first command set and a second command set. The semiconductor memory device performs a charge share operation after the standby mode is released in response to an input of a third command set and a fourth command set during the standby mode. The semiconductor memory device performs the second operation using at least a part of an electric charge generated when the first operation is performed.

Abstract: A semiconductor memory device includes a substrate, first and second P-type well regions on the substrate, an N-type well region on the substrate and sandwiched between the first and second P-type well regions, a first peripheral circuit on a region of the first P-type well region adjacent to the N-type well region and supplied with a reference voltage via a first wiring, and a second peripheral circuit on a region of the second P-type well region adjacent to the N-type well region and supplied with a reference voltage via a second wiring.

Abstract: A semiconductor storage device includes a memory cell array and a voltage generation circuit configured to supply voltages of different levels to the memory cell array. The voltage generation circuit includes a first charge pump having a first characteristic and a second charge pump having a second characteristic that is substantially different from the first characteristic, and is controlled to electrically disconnect an output end of the first charge pump and an input end of the second charge pump in a first operation during which a first voltage is supplied to the memory cell array, and to electrically connect the output end of the first charge pump and the input end of the second charge pump in a second operation during which a second voltage higher than the first voltage is supplied to the memory cell array.

Abstract: A semiconductor storage device includes a memory cell array having a plurality of first conductive layers stacked in a first direction and a plurality of memory cells connected to the plurality of first conductive layers, a wiring layer, and an insulating layer between the memory cell array and the wiring layer and separating the memory cell array and the wiring layer in a second direction intersecting the first direction. The wiring layer includes a plurality of second conductive layers stacked in the first direction, each of the second conductive layers having a corresponding first conductive layer at a same layer, and a contact connected to at least a part of the plurality of second conductive layers and extending in the first direction.

Abstract: A semiconductor storage device includes a first memory chip having a first memory cell, a first word line connected to the first memory cell, a first voltage step-up circuit, and a second voltage step-up circuit, and a second memory chip having a second memory cell, a second word line connected to the second memory cell, a third voltage step-up circuit, and a fourth voltage step-up circuit. During a read operation executed in the first memory chip, the first, second, and fourth voltage step-up circuits supply a first voltage to the first word line, and when a voltage of the first word line reaches a predetermined voltage, the first voltage step-up circuit continues to supply the first voltage to the first word line, and the second voltage step-up circuit and the fourth voltage step-up circuit stop supplying the first voltage to the first word line.

Abstract: A semiconductor device includes a first pad, a comparison circuit, and a control circuit. A first voltage may be applicable to the first pad. The comparison circuit may include a first input terminal connected to the first pad, a second input terminal to which a second voltage is applicable, and an output terminal configured to output a comparison result between the first voltage and the second voltage. The control circuit may be configured to output, external to the semiconductor device, a signal based on the comparison result.

Abstract: A semiconductor storage device includes a memory cell array and a voltage generation circuit configured to supply voltages of different levels to the memory cell array. The voltage generation circuit includes a first charge pump having a first characteristic and a second charge pump having a second characteristic that is substantially different from the first characteristic, and is controlled to electrically disconnect an output end of the first charge pump and an input end of the second charge pump in a first operation during which a first voltage is supplied to the memory cell array, and to electrically connect the output end of the first charge pump and the input end of the second charge pump in a second operation during which a second voltage higher than the first voltage is supplied to the memory cell array.

Abstract: A semiconductor device has a first conductivity type semiconductor substrate. A second conductivity type first impurity diffusion layer is disposed in a surface region of the semiconductor substrate. A resistance element is configured with a first conductivity type second impurity diffusion layer disposed in the first impurity diffusion layer in the surface region of the semiconductor substrate. In a transistor, a gate is connected to an input portion of the resistance element, a source is connected to the first impurity diffusion layer, and a drain is connected to a voltage source higher than the voltage of the input portion. A current source is connected to the source.

Abstract: A semiconductor device includes a first pad, a comparison circuit, and a control circuit. A first voltage may be applicable to the first pad. The comparison circuit may include a first input terminal connected to the first pad, a second input terminal to which a second voltage is applicable, and an output terminal configured to output a comparison result between the first voltage and the second voltage. The control circuit may be configured to output, external to the semiconductor device, a signal based on the comparison result.

Abstract: A semiconductor memory device includes a substrate, first and second P-type well regions on the substrate, an N-type well region on the substrate and sandwiched between the first and second P-type well regions, a first peripheral circuit on a region of the first P-type well region adjacent to the N-type well region and supplied with a reference voltage via a first wiring, and a second peripheral circuit on a region of the second P-type well region adjacent to the N-type well region and supplied with a reference voltage via a second wiring.

Abstract: A semiconductor memory device includes a substrate, first and second P-type well regions on the substrate, an N-type well region on the substrate and sandwiched between the first and second P-type well regions, a first peripheral circuit on a region of the first P-type well region adjacent to the N-type well region and supplied with a reference voltage via a first wiring, and a second peripheral circuit on a region of the second P-type well region adjacent to the N-type well region and supplied with a reference voltage via a second wiring.

Abstract: A semiconductor memory device includes a substrate, first and second P-type well regions on the substrate, an N-type well region on the substrate and sandwiched between the first and second P-type well regions, a first peripheral circuit on a region of the first P-type well region adjacent to the N-type well region and supplied with a reference voltage via a first wiring, and a second peripheral circuit on a region of the second P-type well region adjacent to the N-type well region and supplied with a reference voltage via a second wiring.

Abstract: A semiconductor memory device comprises a first memory cell array including a first memory cell and a second memory cell array including a second memory cell, a first transistor electrically connectable to a first end of the first memory cell via a first source line, a second transistor connectable to a first end of the second memory cell via a second source line, a pad supplied with a reference voltage from outside, a first wiring that electrically connects the first transistor and the pad, and a second wiring that is different from the first wiring and electrically connects the second transistor and the pad.

Abstract: A semiconductor memory device comprises a first memory cell array including a first memory cell and a second memory cell array including a second memory cell, a first transistor electrically connectable to a first end of the first memory cell via a first source line, a second transistor connectable to a first end of the second memory cell via a second source line, a pad supplied with a reference voltage from outside, a first wiring that electrically connects the first transistor and the pad, and a second wiring that is different from the first wiring and electrically connects the second transistor and the pad.

Abstract: According to one embodiment, a voltage generation circuit includes: a charge pump circuit configured to boost a voltage input to a first node and output a first signal to a second node; an operational amplifier configured to receive a first reference voltage and a first voltage obtained by dividing a voltage of the second node and output a second signal to a third node; a first transistor having a gate coupled to the third node, one terminal coupled to a power supply, and the other terminal coupled to the first node; a logic circuit configured to detect the voltage of the second node and output a third signal; and a charge-up circuit configured to receive the third signal and charge a voltage of the third node.

Abstract: According to one embodiment, a voltage generation circuit includes: a charge pump circuit configured to boost a voltage input to a first node and output a first signal to a second node; an operational amplifier configured to receive a first reference voltage and a first voltage obtained by dividing a voltage of the second node and output a second signal to a third node; a first transistor having a gate coupled to the third node, one terminal coupled to a power supply, and the other terminal coupled to the first node; a logic circuit configured to detect the voltage of the second node and output a third signal; and a charge-up circuit configured to receive the third signal and charge a voltage of the third node.

Abstract: According to one embodiment, a voltage generator includes a step-up circuit and a limiter circuit. The step-up circuit outputs a first voltage to a first node. The limiter circuit includes first and second resistive elements, first and second capacitive elements, a switch element, and a comparator. The first resistive element is between the first node and a second node. The second resistive element is connected to the second node. The first capacitive element is between the first and second nodes. The switch element connects the second capacitive element to the second node at the same time that the first node is connected to a load. The comparator compares the potential at the second node with a reference potential.

Abstract: According to one embodiment, a voltage generator includes a step-up circuit and a limiter circuit. The step-up circuit outputs a first voltage to a first node. The limiter circuit includes first and second resistive elements, first and second capacitive elements, a switch element, and a comparator. The first resistive element is between the first node and a second node. The second resistive element is connected to the second node. The first capacitive element is between the first and second nodes. The switch element connects the second capacitive element to the second node at the same time that the first node is connected to a load. The comparator compares the potential at the second node with a reference potential.