Abstract: A packet processing device includes: a non-priority packet storage that stores the non-priority packet; a gate provided on an output side of the non-priority packet storage; plural priority packet storages that respectively store the priority packet; a distributer that guides a received priority packet to a priority packet storage corresponding to a delay time of a route through which the received priority packet is transmitted; a timing setting unit that sets different read cycles to respective priority packet storages; a read controller that reads priority packets from the plural priority packet storages according to the read cycles; and a gate controller that controls the gate according to the timings on which the read priority packets are output. When the read controller reads a first priority packet from one of the priority packet storages, the read controller reads a second priority packet from another priority packet storage.

Abstract: A packet processing device includes: a non-priority packet storage that stores the non-priority packet; a gate provided on an output side of the non-priority packet storage; plural priority packet storages that respectively store the priority packet; a distributer that guides a received priority packet to a priority packet storage corresponding to a delay time of a route through which the received priority packet is transmitted; a timing setting unit that sets different read cycles to respective priority packet storages; a read controller that reads priority packets from the plural priority packet storages according to the read cycles; and a gate controller that controls the gate according to the timings on which the read priority packets are output. When the read controller reads a first priority packet from one of the priority packet storages, the read controller reads a second priority packet from another priority packet storage.

Abstract: A transmission apparatus includes a memory, and a processor coupled to the memory and configured to process communication performed via logical-links established between the transmission apparatus and ONUs coupled to branch ends of a transmission line, perform, for each of the logical-links, a setting process for the communication for the ONUs, acquire, after the setting process, processing-information relating to processing of the communication from the ONUs for each of the logical-links, and store the processing-information in a database, acquire, in accordance with timings at which the logical-links have been re-established after disconnection, processing-information of the logical-links from the ONUs, and make a comparison of the processing-information with the processing-information stored in the database, and omit, in accordance with a result of the comparison, part of the setting process for the logical-links for which the processing-information acquired from the ONUs coincide with the processing-infor

Abstract: A system includes first, second, and third apparatuses. The second apparatus converts a first control-command received from the first apparatus to second control-commands compatible with the third apparatus, requests the third apparatus to perform the second control-commands, and notifies the first apparatus of a normal finish of the first control-command when all the second control-commands have finished normally, so that the first apparatus updates a first status of the third apparatus that is held by the first apparatus.

Abstract: A packet transfer method includes requesting a terminal apparatus for a physical address corresponding to a logical address of a transmission source of a packet; determining legality of a correspondence relationship between the physical address and the logical address by comparing a physical address indicated by a response from the terminal apparatus with the physical address of the transmission source of the packet; storing a first set of the physical address of the transmission source and the logical address of the transmission source of the packet, when it is determined that the correspondence relationship is legal; when a new packet is received, determining whether a second set of a physical address of a transmission source and a logical address of the transmission source of the new packet coincides with the first set; and transferring the new packet, when it is determined that the second set coincides with the first set.

Abstract: A system includes first, second, and third apparatuses. The second apparatus converts a first control-command received from the first apparatus to second control-commands compatible with the third apparatus, requests the third apparatus to perform the second control-commands, and notifies the first apparatus of a normal finish of the first control-command when all the second control-commands have finished normally, so that the first apparatus updates a first status of the third apparatus that is held by the first apparatus.

Abstract: The present invention is comprised for pre-setting bandwidth control information of each user for each of the number of normal physical links which are integrated as a Link Aggregation, recognizing the number of currently normal physical links if a failure, or recovery therefrom, of a physical link which is integrated as the aforementioned Link Aggregation, and carrying out a bandwidth control, for each user traffic, corresponding to the number of the recognized normal physical links by referring to bandwidth control information of each user for each of the number of preset normal physical links, in order to prevent an occurrence of unfairness in usable bandwidth among the users even in the case of a failure occurrence in respective physical links which are logically integrated as a Link Aggregation.

Abstract: In order to rapidly restoration at a time of fault occurrence without lowering usage efficiency of circuit resources, in a configuration in which a plurality of physical circuits are grouped and communication is carried out with transmission data being distributed, a circuit having the minimum traffic from among the grouped circuits is set as a standby circuit, and, a traffic in a fault circuit is transferred to the standby circuit in a lump when a fault occurs in another working circuit.

Abstract: An information processing apparatus having a multitask operating system includes a high-load continuation detecting part detecting continuation of a high-load state of a CPU; a task switching history storing part storing a history of task switching operation; and a trouble task candidate extracting part extracting candidates for a trouble task which causes continuation of a high-load state of the CPU by referring to the history of the task switching operation stored by the task switching history storing part when the continuation of the high-load state of the CPU is detected by the high-load continuation detecting part.

Abstract: The present invention is comprised for pre-setting bandwidth control information of each user for each of the number of normal physical links which are integrated as a Link Aggregation, recognizing the number of currently normal physical links if a failure, or recovery therefrom, of a physical link which is integrated as the aforementioned Link Aggregation, and carrying out a bandwidth control, for each user traffic, corresponding to the number of the recognized normal physical links by referring to bandwidth control information of each user for each of the number of preset normal physical links, in order to prevent an occurrence of unfairness in usable bandwidth among the users even in the case of a failure occurrence in respective physical links which are logically integrated as a Link Aggregation.

Abstract: In order to rapidly restoration at a time of fault occurrence without lowering usage efficiency of circuit resources, in a configuration in which a plurality of physical circuits are grouped and communication is carried out with transmission data being distributed, a circuit having the minimum traffic from among the grouped circuits is set as a standby circuit, and, a traffic in a fault circuit is transferred to the standby circuit in a lump when a fault occurs in another working circuit.

Abstract: A program file management system capable of efficient management of multiple program files, thus permitting reduction in scale of the system and improving convenience. A memory has a starting area and a saving area, and a CPU section performs a switchover from the saving area to the starting area and executes operation in accordance with a program file stored in the starting area. In response to a program file store instruction, the CPU section transfers the program file under execution to the saving area of another unit to be stored therein in accordance with table information. A table database holds an address management table and a destination CPU selection table. An operation management section performs interfacing of commands from the user and performs control including downloading of program files to the CPU unit, registration of the table information in the table database and issuance of the program file store instruction.