Abstract: A non-aqueous electrolyte secondary battery that has a low initial resistance and an increase in resistance after charging and discharging is suppressed. The secondary battery includes a positive electrode, a negative electrode, and a non-aqueous electrolyte. The positive electrode includes a positive electrode active substance layer, which contains a lithium composite oxide having a layered structure. The lithium composite oxide is a porous particle. A surface of the porous particle includes a layer having a rock salt type structure. A thickness of the layer is not less than 5 nm and not more than 80 nm. A void ratio of the porous particle is not less than 15% and not more than 48%. The porous particle contains two or more voids having diameters that are at least 10% of the particle diameter of the porous particle. The surface of the porous particle includes a coating of lithium tungstate.

Abstract: A non-aqueous electrolyte secondary battery is obtained using a lithium composite oxide having a layered structure in a positive electrode active substance. An increase in resistance following repeated charging and discharging is suppressed. The battery includes a positive electrode provided with a positive electrode active substance layer, a negative electrode and a non-aqueous electrolyte. The positive electrode active substance layer contains a porous particle lithium composite oxide having a layered structure. The average void ratio of the porous particle is not less than 12% but not more than 50%, and it contains two or more voids having diameters that are at least 8% of its particle diameter. The surface of the porous particle is provided with a coating of lithium tungstate. The coverage ratio of the surface of the porous particle by the lithium tungstate is not less than 10% but not more than 65%.

Abstract: A non-aqueous electrolyte secondary battery is obtained using a lithium composite oxide having a layered structure in a positive electrode active substance. An increase in resistance following repeated charging and discharging is suppressed. The battery includes a positive electrode provided with a positive electrode active substance layer, a negative electrode and a non-aqueous electrolyte. The positive electrode active substance layer contains a porous particle lithium composite oxide having a layered structure. The average void ratio of the porous particle is not less than 12% but not more than 50%, and it contains two or more voids having diameters that are at least 8% of its particle diameter. The surface of the porous particle is provided with a coating of lithium tungstate. The coverage ratio of the surface of the porous particle by the lithium tungstate is not less than 10% but not more than 65%.

Abstract: A non-aqueous electrolyte secondary battery which is obtained using a lithium composite oxide having a layered structure and coated with a tungsten-containing compound in a positive electrode active substance, and which has a low initial resistance, and in which an increase in resistance following repeated charging and discharging is suppressed. The non-aqueous electrolyte secondary battery includes a positive electrode, a negative electrode and a non-aqueous electrolyte. The positive electrode includes a positive electrode active substance layer containing a lithium composite oxide having a layered structure. The lithium composite oxide includes a porous particle having a void ratio of not less than 20% but not more than 50%. The porous particle contains two or more voids having diameters that are at least 10% of the particle diameter of the porous particle. The surface of the porous particle is provided with a coating containing tungsten oxide and lithium tungstate.

Abstract: An improvement is achieved in the mounting reliability of a semiconductor device. A semiconductor chip is mounted over an upper surface of a wiring substrate. A plurality of solder balls are disposed individually over a plurality of lands formed on a lower surface of the wiring substrate. The plural lands include a first land group arranged in a plurality of rows and arranged along a peripheral edge portion of the lower surface of the wiring substrate, and a second land group arranged inside the first land group in the lower surface of the wiring substrate. The lands in the first land group are arranged with a first pitch, and the lands in the second land group are arranged with a second pitch higher than the first pitch.

Abstract: An improvement is achieved in the mounting reliability of a semiconductor device. A semiconductor chip is mounted over an upper surface of a wiring substrate. A plurality of solder balls are disposed individually over a plurality of lands formed on a lower surface of the wiring substrate. The plural lands include a first land group arranged in a plurality of rows and arranged along a peripheral edge portion of the lower surface of the wiring substrate, and a second land group arranged inside the first land group in the lower surface of the wiring substrate. The lands in the first land group are arranged with a first pitch, and the lands in the second land group are arranged with a second pitch higher than the first pitch.

Abstract: An improvement is achieved in the mounting reliability of a semiconductor device. A semiconductor chip is mounted over an upper surface of a wiring substrate. A plurality of solder balls are disposed individually over a plurality of lands formed on a lower surface of the wiring substrate. The plural lands include a first land group arranged in a plurality of rows and arranged along a peripheral edge portion of the lower surface of the wiring substrate, and a second land group arranged inside the first land group in the lower surface of the wiring substrate. The lands in the first land group are arranged with a first pitch, and the lands in the second land group are arranged with a second pitch higher than the first pitch.

Abstract: An improvement is achieved in the mounting reliability of a semiconductor device. A semiconductor chip is mounted over an upper surface of a wiring substrate. A plurality of solder balls are disposed individually over a plurality of lands formed on a lower surface of the wiring substrate. The plural lands include a first land group arranged in a plurality of rows and arranged along a peripheral edge portion of the lower surface of the wiring substrate, and a second land group arranged inside the first land group in the lower surface of the wiring substrate. The lands in the first land group are arranged with a first pitch, and the lands in the second land group are arranged with a second pitch higher than the first pitch.

Abstract: A semiconductor device having a first semiconductor chip with an SDRAM and a second semiconductor chip with a an MPU controlling the SDRAM. The contour size of the semiconductor device is reduced to a smaller size without impairing the testability of the first semiconductor chip. The two semiconductor chips are stacked over the top surface of an interconnect substrate and sealed in a molding resin, thus forming an SiP (System-in-Package). First terminals electrically connected with the second chip are arranged as external terminals of the SiP on the outer periphery of the bottom surface of the interconnect substrate. Plural second electrodes electrically connected with interconnects, which electrically connect the two chips, are mounted as terminals for testing of the SDRAM. The second electrodes are located more inwardly than the innermost row of the first external electrodes on the bottom surface of the interconnect substrate.

Abstract: A semiconductor device having a first semiconductor chip with an SDRAM and a second semiconductor chip with a an MPU controlling the SDRAM. The contour size of the semiconductor device is reduced to a smaller size without impairing the testability of the first semiconductor chip. The two semiconductor chips are stacked over the top surface of an interconnect substrate and sealed in a molding resin, thus forming an SiP (System-in-Package). First terminals electrically connected with the second chip are arranged as external terminals of the SiP on the outer periphery of the bottom surface of the interconnect substrate. Plural second electrodes electrically connected with interconnects, which electrically connect the two chips, are mounted as terminals for testing of the SDRAM. The second electrodes are located more inwardly than the innermost row of the first external electrodes on the bottom surface of the interconnect substrate.

Abstract: There is disclosed a semiconductor device having first and second semiconductor chips. The first semiconductor chip has a memory circuit. The second semiconductor chip has a circuit controlling the memory circuit. The contour size of the semiconductor device is reduced down to a smaller size required by a client without impairing the testability of the first semiconductor chip having the memory circuit. The circuit controlling the memory circuit consists of an MPU. The memory circuit consists of an SDRAM. The two semiconductor chips are stacked on top of each other over the top surface of an interconnect substrate. The chips are sealed in a molding resin, thus forming an SiP (System-in-Package). First terminals electrically connected with the second chip are arranged as external terminals of the SiP on the outer periphery of the bottom surface of the interconnect substrate.

Abstract: There is disclosed a semiconductor device having first and second semiconductor chips. The first semiconductor chip has a memory circuit. The second semiconductor chip has a circuit controlling the memory circuit. The contour size of the semiconductor device is reduced down to a smaller size required by a client without impairing the testability of the first semiconductor chip having the memory circuit. The circuit controlling the memory circuit consists of an MPU. The memory circuit consists of an SDRAM. The two semiconductor chips are stacked on top of each other over the top surface of an interconnect substrate. The chips are sealed in a molding resin, thus forming an SiP (System-in-Package). First terminals electrically connected with the second chip are arranged as external terminals of the SiP on the outer periphery of the bottom surface of the interconnect substrate.

Abstract: A reduction in a size of a multichip module having a plurality of chips (higher-density mounting) and improvements in the reliability and functionality thereof are intended. By alternately repeating stacking in layers and processing of insulating films and conductive films, a microcomputer chip is face-down bonded to an upper portion of a wiring substrate having build-up substrate portions formed with wires with a surface of the microcomputer chip formed with a bump electrode facing downward. Memory chips are bonded onto an upper portion of the microcomputer chip with the respective surfaces thereof formed with bonding pads and the like facing upward. The bonding pads and the like are connected to bonding pads along edges of the wiring substrate with conductive wires. By thus disposing the microcomputer chip having multifunctionality and a larger number of terminals in a lower layer, the size reduction of a device and the like can be achieved.

Abstract: A reduction in a size of a multichip module having a plurality of chips (higher-density mounting) and improvements in the reliability and functionality thereof are intended. By alternately repeating stacking in layers and processing of insulating films and conductive films, a microcomputer chip is face-down bonded to an upper portion of a wiring substrate having build-up substrate portions formed with wires with a surface of the microcomputer chip formed with a bump electrode facing downward. Memory chips are bonded onto an upper portion of the microcomputer chip with the respective surfaces thereof formed with bonding pads and the like facing upward. The bonding pads and the like are connected to bonding pads along edges of the wiring substrate with conductive wires. By thus disposing the microcomputer chip having multifunctionality and a larger number of terminals in a lower layer, the size reduction of a device and the like can be achieved.