Patents by Inventor Yoshinari Ichihashi
Yoshinari Ichihashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20190181291Abstract: A method for manufacturing a solar cell, including: a step for irradiating a semiconductor substrate to cause the surface to become amorphous and to form an intrinsic amorphous layer, a first conductivity-type layer, and a second conductivity-type layer; and a step for introducing hydrogen into the intrinsic amorphous layer, the first conductivity-type layer, and the second conductivity-type layer.Type: ApplicationFiled: February 19, 2019Publication date: June 13, 2019Applicant: Panasonic Intellectual Property Management Co., Ltd.Inventors: Tsuyoshi Takahama, Wataru Shinohara, Yoshinari Ichihashi, Naoki Yoshimura
-
Patent number: 10026853Abstract: A semiconductor substrate of any one of a first conductivity type and a second conductivity type includes a first main surface and a second main surface. A first semiconductor layer of the first conductivity type is provided on the first main surface. A second semiconductor layer of the second conductivity type is provided on the first main surface. A first electrode is electrically connected to the first semiconductor layer. A second electrode is electrically connected to the second semiconductor layer. An insulating layer comprises silicon nitride and is arranged between the first semiconductor layer and the second semiconductor layer in an overlap region where the second semiconductor layer is provided above the first semiconductor layer. An anti-diffusion film is arranged between the insulating layer and the first semiconductor layer and is configured to prevent nitrogen from diffusing from the insulating layer into the first semiconductor layer.Type: GrantFiled: May 29, 2015Date of Patent: July 17, 2018Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Yoshinari Ichihashi, Motohide Kai
-
Publication number: 20150349146Abstract: A semiconductor substrate of any one of a first conductivity type and a second conductivity type includes a first main surface and a second main surface. A first semiconductor layer of the first conductivity type is provided on the first main surface. A second semiconductor layer of the second conductivity type is provided on the first main surface. A first electrode is electrically connected to the first semiconductor layer. A second electrode is electrically connected to the second semiconductor layer. An insulating layer comprises silicon nitride and is arranged between the first semiconductor layer and the second semiconductor layer in an overlap region where the second semiconductor layer is provided above the first semiconductor layer. An anti-diffusion film is arranged between the insulating layer and the first semiconductor layer and is configured to prevent nitrogen from diffusing from the insulating layer into the first semiconductor layer.Type: ApplicationFiled: May 29, 2015Publication date: December 3, 2015Inventors: Yoshinari ICHIHASHI, Motohide KAI
-
Patent number: 8149051Abstract: A solid-state image sensor capable of suppressing color mixture while suppressing increase of load capacitances of transfer gates and a short circuit between two adjacent transfer gates is provided. This solid-state image sensor comprises a plurality of transfer gates and a shielding material line blocking light incident from above a prescribed pixel upon another pixel adjacent to the prescribed pixel. The shielding material line has a downward projecting portion on a region corresponding to at least one transfer gate entering an ON-state in photoreception.Type: GrantFiled: January 27, 2006Date of Patent: April 3, 2012Assignee: Semiconductor Components Industries, LLCInventors: Yoshinari Ichihashi, Ryu Shimizu, Kazuhiro Sasada
-
Publication number: 20100085997Abstract: A nitride-based semiconductor laser device includes a nitride-based semiconductor layer formed on an active layer made of a nitride-based semiconductor, and an electrode layer including a first metal layer, made of Pt, formed on a far side of a surface of the nitride-based semiconductor layer from the active layer, a second metal layer, made of Pd, formed on a surface of the first metal layer, and a third metal layer, made of Pt, formed on a surface of the second metal layer, and having a shape necessary for the device in plan view. A thickness of the third metal layer is at least 10 times and not more than 30 times a thickness of the first metal layer.Type: ApplicationFiled: October 7, 2009Publication date: April 8, 2010Applicant: Sanyo Electric Co., Ltd.Inventors: Gaku Nishikawa, Kiyoshi Oota, Yoshinari Ichihashi
-
Patent number: 7172962Abstract: On a substrate are sequentially formed a first interconnection 203, a diffusion barrier film 205 and a second insulating film 207, and on the upper surface of the second insulating film 207 is then formed a sacrificial film 213. Next, a via hole 211 and an interconnection trench 217 are formed, and on the sacrificial film 213 are then formed a barrier metal film 219 and a copper film 221. CMP for removing the extraneous copper film 221 and barrier metal film 219 are conducted in a two-step process, i. e., the first polishing where polishing is stopped on the surface of the barrier metal film 219 and the second polishing where the remaining barrier metal film 219 and the tapered sacrificial film 213 are polished.Type: GrantFiled: December 1, 2003Date of Patent: February 6, 2007Assignee: Sanyo Electric Co., Ltd.Inventors: Yoshio Okayama, Hayato Nakashima, Yoshinari Ichihashi
-
Publication number: 20060170007Abstract: A solid-state image sensor capable of suppressing color mixture while suppressing increase of load capacitances of transfer gates and a short circuit between two adjacent transfer gates is provided. This solid-state image sensor comprises a plurality of transfer gates and a shielding material line blocking light incident from above a prescribed pixel upon another pixel adjacent to the prescribed pixel. The shielding material line has a downward projecting portion on a region corresponding to at least one transfer gate entering an ON-state in photoreception.Type: ApplicationFiled: January 27, 2006Publication date: August 3, 2006Inventors: Yoshinari Ichihashi, Ryu Shimizu, Kazuhiro Sasada
-
Patent number: 7052989Abstract: A semiconductor device capable of compatibly suppressing a microloading effect (irregular etching) and over-etching also in formation of a fine contact hole requiring a high aspect ratio is obtained. This semiconductor device comprises a first conductive part, an insulator film having an opening formed on the first conductive part and a second conductive part electrically connected with the first conductive part through the opening. The insulator film includes an upper insulator film and a lower insulator film, stacked/formed at least around a connection part between the first conductive part and the second conductive part, consisting of different materials.Type: GrantFiled: July 23, 2003Date of Patent: May 30, 2006Assignee: Sanyo Electric Co., Ltd.Inventors: Yoshinari Ichihashi, Takashi Goto
-
Publication number: 20050045993Abstract: When a plurality of through holes is formed in a interlayer dielectric film including Si, O, and C at least, a plurality of dummy through holes is formed in the circumference of a cluster of through holes and an isolated through hole. And/or the etching-gas with a higher content of a nitrogenous gas is used, and the etching is performed step by step using the etching gases containing C4F6 and not containing C4F6. And/or the carbon content ratio in the etching gas defined by p=X×(Qc/Q)×100 where X is a carbon component ratio X in a fluorocarbon gas represented by CXFY, Q is a total flow rate of the etching gas, and Qc is a gas flow rate of fluorocarbon CXFY, is set to 5% or less.Type: ApplicationFiled: August 11, 2004Publication date: March 3, 2005Inventors: Michinori Okuda, Yoshinari Ichihashi, Yoshikazu Yamaoka, Yasunori Inoue, Yuko Tanaka
-
Patent number: 6849550Abstract: A method for manufacturing a semiconductor device that forms a connection hole with high electric reliability even when the semiconductor device is designed to be highly integrated. The semiconductor device includes a lower layer wiring and an interlayer insulation film, which is formed on the lower layer wiring and has a connection hole connected with the lower layer wiring. The method includes forming the connection hole by etching the interlayer insulation film. The connection hole is formed by etching part of the lower layer wiring under a first etching condition through physical reaction in at least the vicinity of the lower layer wiring, and by etching part of the interlayer insulation film under a second etching condition that guarantees a selective ratio relative to the lower layer wiring.Type: GrantFiled: July 9, 2002Date of Patent: February 1, 2005Assignee: Sanyo Electric Co. Ltd.Inventors: Yoshinari Ichihashi, Norihiro Ikeda, Takashi Gotou, Ryousuke Usui, Tatsuya Fujishima
-
Publication number: 20040110370Abstract: On a substrate are sequentially formed a first interconnection 203, a diffusion barrier film 205 and a second insulating film 207, and on the upper surface of the second insulating film 207 is then formed a sacrificial film 213. Next, a via hole 211 and an interconnection trench 217 are formed, and on the sacrificial film 213 are then formed a barrier metal film 219 and a copper film 221. CMP for removing the extraneous copper film 221 and barrier metal film 219 are conducted in a two-step process, i. e., the first polishing where polishing is stopped on the surface of the barrier metal film 219 and the second polishing where the remaining barrier metal film 219 and the tapered sacrificial film 213 are polished.Type: ApplicationFiled: December 1, 2003Publication date: June 10, 2004Applicant: Sanyo Electric Co., Ltd.Inventors: Yoshio Okayama, Hayato Nakashima, Yoshinari Ichihashi
-
Publication number: 20040048489Abstract: A semiconductor device capable of compatibly suppressing a microloading effect (irregular etching) and over-etching also in formation of a fine contact hole requiring a high aspect ratio is obtained. This semiconductor device comprises a first conductive part, an insulator film having an opening formed on the first conductive part and a second conductive part electrically connected with the first conductive part through the opening. The insulator film includes an upper insulator film and a lower insulator film, stacked/formed at least around a connection part between the first conductive part and the second conductive part, consisting of different materials.Type: ApplicationFiled: July 23, 2003Publication date: March 11, 2004Applicant: SANYO ELECTRIC CO., LTD.Inventors: Yoshinari Ichihashi, Takashi Goto
-
Publication number: 20030060053Abstract: A method for manufacturing a semiconductor device that forms a connection hole with high electric reliability even when the semiconductor device is designed to be highly integrated. The semiconductor device includes a lower layer wiring and an interlayer insulation film, which is formed on the lower layer wiring and has a connection hole connected with the lower layer wiring. The method includes forming the connection hole by etching the interlayer insulation film. The connection hole is formed by etching part of the lower layer wiring under a first etching condition through physical reaction in at least the vicinity of the lower layer wiring, and by etching part of the interlayer insulation film under a second etching condition that guarantees a selective ratio relative to the lower layer wiring.Type: ApplicationFiled: July 9, 2002Publication date: March 27, 2003Inventors: Yoshinari Ichihashi, Norihiro Ikeda, Takashi Gotou, Ryousuke Usui, Tatsuya Fujishima
-
Publication number: 20010053572Abstract: A semiconductor device capable of compatibly suppressing a microloading effect (irregular etching) and over-etching also in formation of a fine contact hole requiring a high aspect ratio is obtained. This semiconductor device comprises a first conductive part, an insulator film having an opening formed on the first conductive part and a second conductive part electrically connected with the first conductive part through the opening. The insulator film includes an upper insulator film and a lower insulator film, stacked/formed at least around a connection part between the first conductive part and the second conductive part, consisting of different materials.Type: ApplicationFiled: February 21, 2001Publication date: December 20, 2001Inventors: Yoshinari Ichihashi, Takashi Goto