Abstract: An authentication apparatus of embodiments has a counter circuit and a pseudo-pass generating circuit. The counter circuit counts the number of times an inputted cryptographic key and a cryptographic key set in advance consecutively do not match. The pseudo-pass generating circuit outputs a pseudo-pass response when the number of times the keys consecutively do not match, which is counted by the counter circuit, exceeds a predetermined value.

Abstract: An authentication apparatus of embodiments has a counter circuit and a pseudo-pass generating circuit. The counter circuit counts the number of times an inputted cryptographic key and a cryptographic key set in advance consecutively do not match. The pseudo-pass generating circuit outputs a pseudo-pass response when the number of times the keys consecutively do not match, which is counted by the counter circuit, exceeds a predetermined value.

Abstract: An arctangent detector according to the present invention generates a demodulated signal based on the result of arctangent calculation of the ratio between an in-phase component and a quadrature component obtained from a frequency modulation (FM) received signal that are perpendicular to each other. A median filter substitutes the median value of the sample values obtained by sampling the demodulated signal generated by the arctangent detector as many times as the point number for the current value of the demodulated signal and outputs a resultant signal. The point number altering unit alters the point number in the median filter based on the signal intensity of the FM received signal.

Abstract: An arctangent detector according to the present invention generates a demodulated signal based on the result of arctangent calculation of the ratio between an in-phase component and a quadrature component obtained from a frequency modulation (FM) received signal that are perpendicular to each other. A median filter substitutes the median value of the sample values obtained by sampling the demodulated signal generated by the arctangent detector as many times as the point number for the current value of the demodulated signal and outputs a resultant signal. The point number altering unit alters the point number in the median filter based on the signal intensity of the FM received signal.

Abstract: A sampling frequency conversion device comprises an internal circuit for executing in synchronization with an internal clock a signal processing of input data fetched in accordance with an input word clock, and for outputting the input data having undergone the signal processing as output data, a clock generation circuit for generating from the internal clock an output word clock and a counter clock having a frequency which is equal to that of the output word clock multiplied by n (n: integer equal to two or more), a counter for counting the counter clock, and a register for holding a counter value of the counter in synchronization with the input word clock, and for outputting the held counter value to the internal circuit.

Abstract: A semiconductor integrated circuit disclosed herein comprising: a phase control circuit which shifts a phase of a first clock signal based on a phase control signal and outputs a second clock signal; a first flip-flop to which one of the first clock signal and the second clock signal is inputted as a first operation clock signal, and which outputs evaluation data; a circuit under test which performs a predetermined process based on the evaluation data and outputs a result of the process as output data; and a second flip-flop to which the other of the first clock signal and the second clock signal is inputted as a second operation clock signal and the output data is inputted, and which outputs the output data inputted from the circuit under test.

Abstract: A sampling frequency conversion device comprises an internal circuit for executing in synchronization with an internal clock a signal processing of input data fetched in accordance with an input word clock, and for outputting the input data having undergone the signal processing as output data, a clock generation circuit for generating from the internal clock an output word clock and a counter clock having a frequency which is equal to that of the output word clock multiplied by n (n: integer equal to two or more), a counter for counting the counter clock, and a register for holding a counter value of the counter in synchronization with the input word clock, and for outputting the held counter value to the internal circuit

Abstract: A semiconductor integrated circuit disclosed herein comprising: a phase control circuit which shifts a phase of a first clock signal based on a phase control signal and outputs a second clock signal; a first flip-flop to which one of the first clock signal and the second clock signal is inputted as a first operation clock signal, and which outputs evaluation data; a circuit under test which performs a predetermined process based on the evaluation data and outputs a result of the process as output data; and a second flip-flop to which the other of the first clock signal and the second clock signal is inputted as a second operation clock signal and the output data is inputted, and which outputs the output data inputted from the circuit under test.

Abstract: The present invention discloses reproduction pitch change technology incorporated in audio reproduction system capable of changing reproduction pitch or reproduction time of reproduced sound without causing enlargement of the configuration of the system and complicatedness of its processing and damaging the quality of the reproduced sound. When inputted audio data is converted inversely from frequency region to time region the spectrum of the inputted audio data is shifted on the frequency axis based on a reproduction pitch changing amount and a band width of the audio data after the shift is matched to the band width of the inputted audio data before the shift to obtain a reproduction frequency of the time-series audio data to be outputted.