Abstract: An IP address and a MAC address of each of communication devices connected to a plurality of communication ports provided in a switching hub device are associated in an ARP table. Also, priority information representing the communication priority of each communication device is received, and the received priority information is associated with the MAC address of the communication device. When no IP address of a transmission source included in a data packet received at each communication port exists in the ARP table, the IP address and the MAC address of the transmission source are added to the ARP table and priority information is attached to the ARP table.

Abstract: An IP address and a MAC address of each of communication devices connected to a plurality of communication ports provided in a switching hub device are associated in an ARP table. Also, priority information representing the communication priority of each communication device is received, and the received priority information is associated with the MAC address of the communication device. When no IP address of a transmission source included in a data packet received at each communication port exists in the ARP table, the IP address and the MAC address of the transmission source are added to the ARP table and priority information is attached to the ARP table.

Abstract: A transmission device and an integrated circuit improved in quality and reliability of digital transmission control. A memory stores an input signal, write address generating means generates a write address for writing in the memory, and read address generating means generates a read address for reading from the memory. Phase state monitoring means monitors a transition from a steady phase state in which writing/reading in/from the memory is normally performed or from a startup state to a coincident phase state in which address values of the write and read addresses coincide with each other or to an unstable phase state in which a phase fluctuation margin is one-sided. When the coincident phase state or the unstable phase state is detected, reset signal output means outputs a reset signal to the write and read address generating means such that the phase relation between the write and read addresses is brought to an optimum phase relation.