Patents by Inventor Yoshinari Uetake

Yoshinari Uetake has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5223442
    Abstract: Phosphorus is doped into one of the major surfaces of an n-type silicon semiconductor substrate, and boron is doped into the other major surface. Thereafter, the structure is diffused into the surface regions of the substrate at a high temperature and for a long time, so that an n-buffer layer is formed in the first major surface, and a p-base layer is formed in the second major surface. Impurity of n-type is diffused into the p-base layer, to form an n-emitter layer. Impurity of p-type is diffused into the n-buffer layer, to selectively form p-emitter layer. Further, n-type impurity is diffused into the n-buffer layer, to form n-type anode short layer.
    Type: Grant
    Filed: July 9, 1992
    Date of Patent: June 29, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mitsuhiko Kitagawa, Yoshio Yokota, Kazuo Watanuki, Yoshinari Uetake, Kazunobu Nishitani, Tsuneo Ogura
  • Patent number: 5156981
    Abstract: Phosphorus is doped into one of the major surfaces of an n-type silicon semiconductor substrate, and boron is doped into the other major surface. Thereafter, the structure is diffused into the surface regions of the substrate at a high temperature and for a long time, so that an n-buffer layer is formed in the first major surface, and a p-base layer is formed in the second major surface. Impurity of n-type is diffused into the p-base layer, to form an n-emitter layer. Impurity of p-type is diffused into the n-buffer layer, to selectively form p-emitter layer. Further, n-type impurity is diffused into the n-buffer layer, to form n-type anode short layer.
    Type: Grant
    Filed: April 6, 1989
    Date of Patent: October 20, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mitsuhiko Kitagawa, Yoshio Yokota, Kazuo Watanuki, Yoshinari Uetake, Kazunobu Nishitani, Tsuneo Ogura
  • Patent number: 5028974
    Abstract: A semiconductor switching device includes a high resistance first base layer of n-type formed on a first emitter layer of p-type through a low resistance buffer layer of n.sup.+ -type, second base layer of p-type formed on the first base layer, second emitter layers of n.sup.+ -type separately formed on the second base layer, anode and cathode main electrodes formed in contact with the first and second emitter layers, and a gate electrode formed in contact with the second base layer. Part of the low resistance buffer layer is exposed to the surface of the first emitter layer and is made contact with the anode main electrode to constitute a shorting portion. The width of the shorting portion is set smaller than one tenth of that of the second emitter layer in a longitudinal direction.
    Type: Grant
    Filed: February 5, 1990
    Date of Patent: July 2, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mituhiko Kitagawa, Tsuneo Ogura, Hiromichi Ohashi, Yoshinari Uetake, Yoshio Yokota, Kazuo Watanuki
  • Patent number: 4958215
    Abstract: A press-contact flat type semiconductor device is disclosed which, without alloy-bonding a silicon pellet to a molybdenum or tungsten disc, assures a uniform press contact because a warp on the silicon pellet is largely reduced in comparison with a conventional device. A silver sheet is omitted between an anode electrode post and the silicon pellet to absorb a warp on the pellet. It is only necessary to insert a molybdenum or tungsten disc there, instead, which is thinner than a counterpart of the conventional device.
    Type: Grant
    Filed: July 25, 1989
    Date of Patent: September 18, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinjiro Kojima, Hideo Matsuda, Masami Iwasaki, Yoshinari Uetake
  • Patent number: 4882612
    Abstract: In a power semiconductor device according to the present invention, a sheet, formed of a soft metal such as Ag, is provided on that portion of a pressing control electrode which is brought into contact with an Al gate electrode of a pellet. By means of this sheet, it is possible both to apply a strong pressing power to the Al gate electrode and to reduce the contact resistance between the two electrode. Since an excessive amount of heat is not produced on account of the contact resistance, the semiconductor device can be protected against being damaged.
    Type: Grant
    Filed: May 4, 1987
    Date of Patent: November 21, 1989
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasunori Usui, Hiroshi Okamura, Yoshinari Uetake, Takashi Fujiwara
  • Patent number: 4618877
    Abstract: A mesa type power semiconductor device comprising a mesa groove disposed on the bottom thereof with separated gate electrodes leaving the central portion of the groove bottom free from a gate electrode. This construction is effective in preventing occurrence of an insulator breakdown between a cathode and a gate electrode.
    Type: Grant
    Filed: December 18, 1984
    Date of Patent: October 21, 1986
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Youichi Araki, Yoshinari Uetake