Abstract: A first image data interface section is disposed in an electrode region and an input/output buffer region provided along a first side of a semiconductor chip. A second image data interface section is disposed in an electrode region and an input/output buffer region provided along a second side. A first memory interface section is disposed in an electrode region and an input/output buffer region provided along a third side. A second memory interface section is disposed in an electrode region and an input/output buffer region provided along a fourth side.

Abstract: An image processing device that receives pixel-unit image data in a plurality of frames in time series and performs image processing, the image data being captured by an imaging section, the image processing device including a brightness change detection section that integrates pixel values or pixel components relating to luminance of at least part of pixels of the received image data in each of the frames to calculate an integrated value, compares the integrated value with a given comparison target value, and detects a change in brightness of an image in each of the frames based on a comparison result.

Abstract: A first image data interface section is disposed in an electrode region and an input/output buffer region provided along a first side of a semiconductor chip. A second image data interface section is disposed in an electrode region and an input/output buffer region provided along a second side. A first memory interface section is disposed in an electrode region and an input/output buffer region provided along a third side. A second memory interface section is disposed in an electrode region and an input/output buffer region provided along a fourth side.

Abstract: A floating point computing device having a mantissa register for storing a mantissa of a floating-point number, a detecting circuit for determining the bit states of the consecutive bits of the mantissa register, and a round and normalize data generating circuit for generating, on the basis of the output of the detecting circuit, information for controlling rounding and normalization. The detecting circuit determines whether all the bits of the digits of the mantissa register are 0 or whether they are 1. In response to the output of the detecting circuit, the round and normalize data generating circuit generates information including the kind of rounding operation and a rounding constant. When the resultant mantissa is negative, the kind of computation is indicative of subtraction. Consequently, the complement processing of the mantissa and the rounding operation are executed at the same time.