Patents by Inventor Yoshinobu Arita

Yoshinobu Arita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5785877
    Abstract: An object to be etched is loaded in a low-pressure vapor phase processing chamber, and then an etching gas obtained by adding a small amount of additive gas of oxygen or additive gas at least containing oxygen to a reaction gas used for etching is fed to the low-pressure vapor phase processing chamber so as to suppress a reaction between the wall of the low-pressure vapor phase processing chamber and the reaction gas. In this state, the object to be etched is dry-etched with the etching gas.
    Type: Grant
    Filed: February 11, 1997
    Date of Patent: July 28, 1998
    Assignees: Nippon Telegraph and Telephone Corporation, Tokyo Electron Limited
    Inventors: Masaaki Sato, Yoshinobu Arita, Masahiro Ogasawara, Hidenori Satoh, Hiromitsu Kanbara
  • Patent number: 5723383
    Abstract: According to a semiconductor substrate treatment method, a surface or vicinity of a semiconductor substrate is deactivated by exposing the semiconductor substrate to a plasma atmosphere in which a gas containing at least hydrogen atoms is excited. A treatment is performed on the deactivated substrate surface. The treated substrate surface is activated by heating the semiconductor substrate.
    Type: Grant
    Filed: March 17, 1995
    Date of Patent: March 3, 1998
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Toshihiko Kosugi, Hiromu Ishii, Yoshinobu Arita
  • Patent number: 5462014
    Abstract: Gold or copper is grown on a substrate by a chemical vapor deposition method using a .beta.-ketonato type metal complex of gold or copper as a starting material and introducing the starting material to the substrate using as a carrier gas a mixed gas composed of hydrogen and a substance which can bond to the starting material in a state where electron is donated from the substance to the starting material to form a molecular compound.
    Type: Grant
    Filed: February 23, 1994
    Date of Patent: October 31, 1995
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Nobuyoshi Awaya, Yoshinobu Arita
  • Patent number: 5316796
    Abstract: A chemical vapor deposition process for growing a thin metallic film of copper or gold on a substrate includes providing a starting material composed of a .beta.-ketonato type metal complex of gold or copper in a heated container; preparing a carrier gas for the starting material which is composed of hydrogen as a reducing agent and at least one electron donating substance which bonds to and forms a molecular compound with the starting material by donating an electron to the starting material; passing a flow of the carrier gas through the heated container containing the starting material to form the molecular compound in situ and provide a flow of a gas mixture; introducing the flow of the gas mixture into a reaction chamber in which a substrate is positioned; and growing gold or copper on the substrate by thermally decomposing the molecular compound and any remaining starting material under temperature conditions effective therefor.
    Type: Grant
    Filed: March 7, 1991
    Date of Patent: May 31, 1994
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Nobuyoshi Awaya, Yoshinobu Arita
  • Patent number: 5104694
    Abstract: A selected chemical vapor deposition method includes the steps of arranging a substrate having a silicon surface and an insulator surface in a reaction chamber, supplying a gas consisting of a silicon hydride in said reaction chamber to reduce and remove a native oxide film on said silicon surface by said gas, and supplying a source gas in said reaction chamber to selectively form a film on only said silicon surface.
    Type: Grant
    Filed: April 16, 1990
    Date of Patent: April 14, 1992
    Assignee: Nippon Telephone & Telegraph Corporation
    Inventors: Kunio Saito, Yoshinobu Arita, Takao Amazawa
  • Patent number: 5080927
    Abstract: A thin film formation method includes the steps of holding a substrate in a reduced-pressure vapor phase reaction chamber having means for irradiating light in visible and ultraviolet ranges, supplying an organo-titanium compound containing a tri-azo group, and vapor-depositing a titanium nitride film on a surface of the substrate by an excitation reaction caused by light.
    Type: Grant
    Filed: July 6, 1990
    Date of Patent: January 14, 1992
    Assignee: Nippon Telegraph and Telephone Corp.
    Inventors: Koichi Ikeda, Masahiko Maeda, Yoshinobu Arita
  • Patent number: 5019531
    Abstract: A process for growing a thin metallic film of gold or copper selectively on a predetermined area of a substrate. An organic complex or organometallic compound of gold or copper as a starting material is heated to evaporate the same, while a substrate having on the surface thereof a metal or a metallic silicide as a first material and an oxide or a nitride as a second material is heated at a temperature equal to or higher than the decomposition temperature, on the first material, of a vapor of the starting material. The vapor of the evaporated starting material is fed together with a reducing gas onto the heated substrate to selectively grow a thin metallic film of gold or copper only on the surface of the first material.
    Type: Grant
    Filed: May 19, 1989
    Date of Patent: May 28, 1991
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Nobuyoshi Awaya, Yoshinobu Arita
  • Patent number: 4963242
    Abstract: A plasma etching apparatus a first cathode electrode, an anode electrode, an annular second cathode electrode, a magnetic field applying unit and high-frequency power sources. An object to be etched is placed on the first cathode electrode. The anode electrode is arranged opposite to the first cathode electrode so as to be separated therefrom and connected to a constant potential source. The second cathode electrode is located between the first cathode electrode and the anode electrode and substantially surrounds the first cathode electrode in an insulated state. The magnetic field applying unit includes coils which generate lines of magnetic force passing through the annular second cathode electrode substantially parallel to a surface of the first cathode electrode on which the object to be etched is placed.
    Type: Grant
    Filed: May 19, 1989
    Date of Patent: October 16, 1990
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Masaaki Sato, Yoshinobu Arita
  • Patent number: 4920401
    Abstract: In a bipolar transistor, around the border line of the surface of a base region formed on a semiconductor substrate is formed a base electrode having a constant width of less than one micron and made of polycrystalline silicon. An island shaped emitter region is formed in the base region and an emitter electrode is formed on the surface of the emitter region. The emitter electrode is electrically isolated from the base electrode by an insulating film extending between the periphery of the emitter region and the base electrode.
    Type: Grant
    Filed: March 14, 1985
    Date of Patent: April 24, 1990
    Assignee: Nippon Telegraph & Telephone Public Corp.
    Inventors: Tetsushi Sakai, Yoshizi Kobayasi, Hironori Yamauchi, Yoshinobu Arita
  • Patent number: 4660068
    Abstract: A substrate structure utilized to fabricate a semiconductor device is constituted by a silicon substrate; an element region selectively formed on the silicon substrate and a relatively thick field oxide region formed adjacent to the element region; an element isolating region formed between the element region and the field oxide region, the element isolating region being in direct contact with the field oxide region; the element isolating region being provided with a relatively deep groove formed in the silicon substrate and having a relatively small width; a silicon oxide insulating film formed on the inner wall of the groove; and a silicon nitride insulating film disposed on the silicon oxide insulating film. The surfaces of the element region, the element isolating region and the field oxide region on the silicon substrate are formed substantially flat.
    Type: Grant
    Filed: August 22, 1983
    Date of Patent: April 21, 1987
    Assignee: Nippon Telegraph & Telephone Corporation
    Inventors: Kazuhito Sakuma, Yoshinobu Arita, Masaaki Sato, Nobuyoshi Awaya
  • Patent number: 4531282
    Abstract: In a bipolar transistor, around the border line of the surface of a base region formed on a semiconductor substrate is formed a base electrode having a constant width of less than one micron and made of polycrystalline silicon. An island shaped emitter region is formed in the base region and an emitter electrode is formed on the surface of the emitter region. The emitter electrode is electrically isolated from the base electrode by an insulating film extending between the periphery of the emitter region and the base electrode.
    Type: Grant
    Filed: January 17, 1984
    Date of Patent: July 30, 1985
    Assignee: Nippon Telegraph and Telephone Public Corp.
    Inventors: Tetsushi Sakai, Yoshizi Kobayasi, Hironori Yamauchi, Yoshinobu Arita