Patents by Inventor Yoshinobu Kagawa

Yoshinobu Kagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Redundancy memory circuit
    Publication number: 20020173055
    Abstract: A semiconductor memory chip has fuses and a redundancy memory cell which can replace a normal memory cell that is found defective by cutting off the fuses. If the normal memory cell is defective, the fuses are cut off thereby to connect the redundancy memory cell instead of the normal memory cell which is defective. The entire surface of the semiconductor memory chip is coated with a resist layer. The coated the resist layer is exposed at regions of the fuses to an energy beam, and then developed form a resist pattern. The semiconductor memory chip is etched at the regions using the resist pattern as a mask for thereby cutting off the fuses. The fuses may be spaced at intervals of 2 &mgr;m or smaller, and can be cut off without causing damage to a layer beneath the fuses.
    Type: Application
    Filed: June 28, 2002
    Publication date: November 21, 2002
    Inventors: Naoki Nishio, Hideyuki Fukuhara, Yoichi Miyai, Yoshinobu Kagawa
  • Method of repairing semiconductor memory, electron-beam memory repairing apparatus and redundancy memory circuit to which the method of repairing semiconductor memory is applicable
    Patent number: 6434063
    Abstract: A semiconductor memory chip has fuses and a redundancy memory cell which can replace a normal memory cell that is found defective by cutting off the fuses. If the normal memory cell is defective, the fuses are cut off thereby to connect the redundancy memory cell instead of the normal memory cell which is defective. The entire surface of the semiconductor memory chip is coated with a resist layer. The coated the resist layer is exposed at regions of the fuses to an energy beam, and then developed form a resist pattern. The semiconductor memory chip is etched at the regions using the resist pattern as a mask for thereby cutting off the fuses. The fuses may be spaced at intervals of 2 &mgr;m or smaller, and can be cut off without causing damage to a layer beneath the fuses.
    Type: Grant
    Filed: November 4, 1998
    Date of Patent: August 13, 2002
    Assignee: Advantest Corporation
    Inventors: Naoki Nishio, Hideyuki Fukuhara, Yoichi Miyai, Yoshinobu Kagawa
  • Method of repairing semiconductor memory, electron-beam memory repairing apparatus and redundancy memory circuit to which the method of repairing semiconductor memory is applicable
    Patent number: 5985677
    Abstract: A semiconductor memory chip has fuses and a redundancy memory cell which can replace a normal memory cell that is found defective by cutting off the fuses. If the normal memory cell is defective, the fuses are cut off thereby to connect the redundancy memory cell instead of the normal memory cell which is defective. The entire surface of the semiconductor memory chip is coated with a resist layer. The coated the resist layer is exposed at regions of the fuses to an energy beam, and then developed form a resist pattern. The semiconductor memory chip is etched at the regions using the resist pattern as a mask for thereby cutting off the fuses. The fuses may be spaced at intervals of 2 .mu.m or smaller, and can be cut off without causing damage to a layer beneath the fuses.
    Type: Grant
    Filed: May 21, 1997
    Date of Patent: November 16, 1999
    Assignees: Advantest Corporation, Texas Instruments Japan
    Inventors: Naoki Nishio, Hideyuki Fukuhara, Yoichi Miyai, Yoshinobu Kagawa