Abstract: Speed enhancement of data reading is achieved while suppressing an influence of an offset voltage of a differential amplifier.

Abstract: In accordance with an embodiment, a control circuit includes a multifunction current analysis circuit configured to receive a first current and connected to a charge pump circuit. An output of a charge pump is connected to an input of the multifunction current analysis circuit, and an oscillator control circuit has an input connected to an output of the multifunction current analysis circuit and to an input of the charge pump through an oscillator circuit. In accordance with another embodiment, a method for controlling a voltage of a semiconductor component is provided that includes generating a first current, a second current, and a third current from a charge pump output circuit and comparing the second current level with the third current level to generate a first comparison result. The first comparison result is used to control a frequency of an output signal of an oscillator circuit.

Abstract: A power supply circuit system includes a ring oscillator provided with a variable resistance circuit, a charge pump circuit outputting a boosted voltage in response to an oscillation output signal from the ring oscillator, a voltage regulator circuit adjusting the boosted voltage from the charge pump circuit, a first current comparator circuit comparing a first current flowing through the voltage regulator circuit with a first reference current, a second current comparator circuit comparing the first current with a second reference current, and a control circuit outputting control signals to control a resistance value of the variable resistance circuit in accordance with a first comparison signal from the first current comparator circuit and a second comparison signal from the second current comparator circuit.

Abstract: Whether there is a defect such as chipping of a die or separation of a resin in a wafer level package is electrically detected. A peripheral wiring is disposed along four peripheries of a semiconductor substrate outside a circuit region and pad electrodes P1-P8. The peripheral wiring is formed on the semiconductor substrate and is made of a metal layer that is the same layer as or an upper layer of a metal layer forming the pad electrodes P1-P8, or a polysilicon layer. A power supply electric potential Vcc is applied to a first end of the peripheral wiring, while a ground electric potential Vss is applied to a second end of the peripheral wiring through a resistor R2. A detection circuit is connected to a connecting node N1 between the peripheral wiring and the resistor R2, and is structured to generate an anomaly detection signal ERRFLG based on an electric potential at the connecting node N1.

Abstract: A power supply circuit system includes a ring oscillator provided with a variable resistance circuit, a charge pump circuit outputting a boosted voltage in response to an oscillation output signal from the ring oscillator, a voltage regulator circuit adjusting the boosted voltage from the charge pump circuit, a first current comparator circuit comparing a first current flowing through the voltage regulator circuit with a first reference current, a second current comparator circuit comparing the first current with a second reference current, and a control circuit outputting control signals to control a resistance value of the variable resistance circuit in accordance with a first comparison signal from the first current comparator circuit and a second comparison signal from the second current comparator circuit.

Abstract: The invention decreases the number of writing processes of EEPROM. When a mode change signal is L level, a EEPROM is set to a bank mode. In this case, first and second memory banks are independently accessed by a control signal of a first port and a control signal of a second port, respectively. When the mode change signal is H level, the EEPROM is set to a combine mode. In this case, the first and second memory banks are combined into a 4k-bit memory bank, and accessed by the control signal of the first port.

Abstract: Whether there is a defect such as chipping of a die or separation of a resin in a wafer level package is electrically detected. A peripheral wiring is disposed along four peripheries of a semiconductor substrate outside a circuit region and pad electrodes P1-P8. The peripheral wiring is formed on the semiconductor substrate and is made of a metal layer that is the same layer as or an upper layer of a metal layer forming the pad electrodes P1-P8, or a polysilicon layer. A power supply electric potential Vcc is applied to a first end of the peripheral wiring, while a ground electric potential Vss is applied to a second end of the peripheral wiring through a resistor R2. A detection circuit is connected to a connecting node N1 between the peripheral wiring and the resistor R2, and is structured to generate an anomaly detection signal ERRFLG based on an electric potential at the connecting node N1.

Abstract: An efficient erasure is performed. The voltage of a source line SL is manipulated in units of a sector providing a plurality of memory cells. An erase command is received for the desired memory cells to be erased in a plurality of word line WL units arranged within a sector and all data within the sector, which includes the desired memory cells to be erased, is saved in a separate memory. Erasure is then performed for the entire sector, and among the saved data the data outside the desired memory cells to be erased is returned to the memory cells.

Abstract: The invention is directed to decreasing a circuit size of a system in which a plurality of devices or circuit blocks share and use one memory. A system is configured so that a memory block serves as a master and each of circuit blocks serves as a slave, and thus the slave side (the circuit blocks) receives necessary data from the memory block by only having decoders corresponding to addresses assigned thereto in advance and registers. In this case, since the registers have been also needed in a conventional system in order to hold data read out from a memory, the circuit size decreases in the whole system. Since this effect is enhanced in proportion to the number of the circuit blocks sharing the memory block, the effect is enhanced as the system size increases.

Abstract: The invention decreases the number of writing processes of EEPROM. When a mode change signal is L level, a EEPROM is set to a bank mode. In this case, first and second memory banks are independently accessed by a control signal of a first port and a control signal of a second port, respectively. When the mode change signal is H level, the EEPROM is set to a combine mode. In this case, the first and second memory banks are combined into a 4k-bit memory bank, and accessed by the control signal of the first port.

Abstract: The invention is directed to decreasing a circuit size of a system in which a plurality of devices or circuit blocks share and use one memory. A system is configured so that a memory block serves as a master and each of circuit blocks serves as a slave, and thus the slave side (the circuit blocks) receives necessary data from the memory block by only having decoders corresponding to addresses assigned thereto in advance and registers. In this case, since the registers have been also needed in a conventional system in order to hold data read out from a memory, the circuit size decreases in the whole system. Since this effect is enhanced in proportion to the number of the circuit blocks sharing the memory block, the effect is enhanced as the system size increases.

Abstract: The invention provides a semiconductor memory device which realizes high speed reading by automatically adjusting and optimizing charge and discharge timings even when a change in an operation environment such as a variation in an operation voltage, an operation temperature, a process parameter and so on occurs. First and second dummy bit lines are provided for a bit line, each having a wiring load twice the wiring load of the bit line. A first sense circuit sensing the voltage of the first dummy bit line is provided to control a charging time according to a first sense signal. A second sense circuit sensing the voltage of the second dummy bit line is further provided to control a discharging time according to a second sense signal. A sense amplifier sensing the voltage of the bit line is activated in response to the second sense signal.

Abstract: An efficient erasure is performed. The voltage of a source line SL is manipulated in units of a sector comprising a plurality of memory cells. An erase command is received for the desired memory cells to be erased in a plurality of word line WL units arranged within a sector and all data within the sector, which includes the desired memory cells to be erased, is saved in a separate memory. Erasure is then performed for the entire sector, and among the saved data the data outside the desired memory cells to be erased is returned to the memory cells.

Abstract: The invention provides a semiconductor memory device which realizes high speed reading by automatically adjusting and optimizing charge and discharge timings even when a change in an operation environment such as a variation in an operation voltage, an operation temperature, a process parameter and so on occurs. First and second dummy bit lines are provided for a bit line, each having a wiring load twice the wiring load of the bit line. A first sense circuit sensing the voltage of the first dummy bit line is provided to control a charging time according to a first sense signal. A second sense circuit sensing the voltage of the second dummy bit line is further provided to control a discharging time according to a second sense signal. A sense amplifier sensing the voltage of the bit line is activated in response to the second sense signal.

Abstract: This invention largely reduces a data writing time of a non-volatile semiconductor memory device. A memory array is split into a first memory cell array to be programmed with normal data in its memory cells and a second memory cell array to be programmed with inverted data of the normal data in its memory cells. A column decoder selects a bit line connected with the memory cell written with the normal data and a bit line connected with the memory cell written with the inverted data simultaneously. A differential amplifier amplifies a difference between signals outputted to the pair of these bit lines and outputs it to an I/O line.

Abstract: This invention largely reduces a data writing time of a non-volatile semiconductor memory device. A memory array is split into a first memory cell array to be programmed with normal data in its memory cells and a second memory cell array to be programmed with inverted data of the normal data in its memory cells. A column decoder selects a bit line connected with the memory cell written with the normal data and a bit line connected with the memory cell written with the inverted data simultaneously. A differential amplifier amplifies a difference between signals outputted to the pair of these bit lines and outputs it to an I/O line.

Abstract: To assure collective erasure irrespectively of whether or not there is any faulty sector which is an object for redundancy. A non-volatile semiconductor memory having a plurality of regions of sectors for which collective erasure of stored data can be made, comprising: a high voltage generating circuit 8 for generating a high voltage used for erasing data for the non-volatile semiconductor memory; a plurality of transistors 10A, 10B and 10C each connected between the high voltage generating circuit and the plurality of regions of sectors 9A, 9B and 9C; wherein constant current operation for the plurality of transistors 10A, 10B and 10C is performed for collective erasure of the data so as to limit the current flowing through the plurality of regions of sectors.

Abstract: A semiconductor memory device comprises: memory cells 1 and 2 in which data are stored; capacitor 23 which are connected to the output line 10 of the memory cells 1 and 2 and are discharged according to a sense; and a sense circuit 25 which supplies a discharge current to the said non-volatile memory cell caused by discharge of said capacitor 23 and senses a change of the output voltage of said output line, which is generated according to a data stored in said non-volatile memory (cf. FIG. 1).