Patents by Inventor Yoshinobu Maeno

Yoshinobu Maeno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160254241
    Abstract: A printed circuit board includes: a substrate; a first electrode formed on the substrate; a protrusion member formed on the first electrode and extending from a central portion of the first electrode towards an outer peripheral portion of the first electrode; and a solder covering the first electrode and the protrusion member and connecting the first electrode to a second electrode of a component mounted on the substrate.
    Type: Application
    Filed: January 27, 2016
    Publication date: September 1, 2016
    Applicant: FUJITSU LIMITED
    Inventors: Yoshinobu MAENO, Kinuko MISHIRO
  • Publication number: 20100101848
    Abstract: A substrate unit includes an electronic component having a plurality of electrodes arranged in a given shape, a circuit substrate having a first face where the electronic component is mounted and the electrodes are jointed and a second face underside of the first face, and a resin-coated portion formed on the second face according to a projected area of the second face to which the given shape is projected.
    Type: Application
    Filed: July 8, 2009
    Publication date: April 29, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Yoshinobu Maeno, Keiichi Yamamoto, Masakazu Takesue
  • Publication number: 20080205009
    Abstract: An electronic apparatus includes: a package body that has a tabular outside shape and is packaged with a built-in electronic circuit; a bump that electrically connects the electronic circuit inside the package body to a wiring outside the package body; a wiring board that has a wiring at least on its surface, the wiring board mounted with the package body so that the electronic circuit of the package body is electrically connected to the wiring via the bump; and an adhesive that bonds the package body onto the wiring board so as to bond only an edge of the package body to the wiring board.
    Type: Application
    Filed: December 28, 2007
    Publication date: August 28, 2008
    Applicant: FUJITSU LIMITED
    Inventor: Yoshinobu Maeno
  • Patent number: 6222738
    Abstract: A packaging structure of semiconductor elements and for mounting such elements on which high density pads are formed on a board at a high production yield, where bumps or gold wires are bonded in a staggered manner within a pad on a semiconductor element. The spaces between bumps or gold wires can be widened without changing the semiconductor element.
    Type: Grant
    Filed: March 18, 1998
    Date of Patent: April 24, 2001
    Assignee: Fujitsu Limited
    Inventors: Yoshinobu Maeno, Kenichiro Abe, Kouzi Soekawa