Patents by Inventor Yoshinobu Momma

Yoshinobu Momma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4546537
    Abstract: In a semiconductor device comprising at least one bipolar transistor and a VIP isolating layer which are formed in both an epitaxial layer and a semiconductor substrate, an impurity-introduced region having the same conductivity type as that of the semiconductor substrate is formed so as to surround the V-groove. A buried layer of the bipolar transistor comes into contact with the VIP isolating layer to divide the impurity-introduced region into two parts, one of which is combined with a base region and the other one of which serves as a channel stopper.
    Type: Grant
    Filed: February 10, 1984
    Date of Patent: October 15, 1985
    Assignee: Fujitsu Limited
    Inventors: Yunosuke Kawabe, Yoshinobu Momma
  • Patent number: 4497106
    Abstract: A semiconductor device comprising at least one bipolar transistor and at least one MIS FET integrated in a single semiconductor substrate, has an electrode for each region of the bipolar transistor and the MIS FET. Each electrode has the same conductivity type as the corresponding region and is connected to ohmic contact with the surface of the corresponding region.
    Type: Grant
    Filed: October 28, 1981
    Date of Patent: February 5, 1985
    Assignee: Fujitsu Limited
    Inventors: Yoshinobu Momma, Tsuneo Funatsu, Atusi Sasaki
  • Patent number: 4376664
    Abstract: In a case where a semiconductor device is produced comprising at least one semiconductor element, an isolation region surrounding the semiconductor element and a thick silicon oxide layer lying on and around the semiconductor element, the thick oxide layer is formed by thermal-oxidizing the epitaxial layer having a buried layer and, at the same time, the isolation region is formed in the epitaxial layer by heating for thermal oxidation. Prior to a step of introducing impurities into the epitaxial layer, the epitaxial layer is covered by an anti-oxidation masking layer, an insulating layer and a photo resist layer. Subsequent to the step of introducing impurities, the anti-oxidation masking layer is shaped into a pattern mask for the thermal-oxidation treatment.
    Type: Grant
    Filed: May 30, 1980
    Date of Patent: March 15, 1983
    Assignee: Fujitsu Limited
    Inventors: Osamu Hataishi, Yoshinobu Momma
  • Patent number: 4343080
    Abstract: In a case where a semiconductor device is produced comprising at least one semiconductor element, an isolation region surrounding the semiconductor element and a thick silicon oxide layer lying on and around the semiconductor element, the thick oxide layer is formed by thermally-oxidizing the epitaxial layer having a buried layer and, at the same time, the isolation region is formed in the epitaxial layer by heating for thermal oxidation. Prior to a step of introducing impurities into the epitaxial layer, a patterned thin silicon oxide layer is formed. This thin silicon oxide layer is varied into the thick oxide layer by the thermal-oxidation treatment.
    Type: Grant
    Filed: May 30, 1980
    Date of Patent: August 10, 1982
    Assignee: Fijitsu Limited
    Inventors: Osamu Hataishi, Yoshinobu Momma, Ryoji Abe
  • Patent number: 4231057
    Abstract: An improved means and method for isolating semiconductor devices on a semiconductor substrate, comprising a shallow region formed between the semiconductor substrate and an epitaxial layer of each device, and between a buried layer of each device and an isolation region separating adjacent devices. The shallow region has conductivity type opposite to that of the semiconductor substrate and higher impurity concentration than that of the epitaxial layer.
    Type: Grant
    Filed: November 13, 1978
    Date of Patent: October 28, 1980
    Assignee: Fujitsu Limited
    Inventors: Yoshinobu Momma, Yunosuke Kawabe, Osamu Hataishi
  • Patent number: RE31652
    Abstract: In a case where a semiconductor device is produced comprising at least one semiconductor element, an isolation region surrounding the semiconductor element and a thick silicon oxide layer lying on and around the semiconductor element, the thick oxide layer is formed by thermally-oxidizing the epitaxial layer having a buried layer and, at the same time, the isolation region is formed in the epitaxial layer by heating for thermal oxidation. Prior to a step of introducing impurities into the epitaxial layer, a patterned thin silicon oxide layer is formed. This thin silicon oxide layer is varied into the thick oxide layer by the thermal-oxidation treatment.
    Type: Grant
    Filed: August 29, 1983
    Date of Patent: August 28, 1984
    Assignee: Fujitsu Limited
    Inventors: Osamu Hataishi, Yoshinobu Momma, Ryoji Abe
  • Patent number: RE31937
    Abstract: An improved means and method for isolating semiconductor devices on a semiconductor substrate, comprising a shallow region formed between the semiconductor substrate and an epitaxial layer of each device, and between a buried layer of each device and an isolation region separating adjacent devices. The shallow region has conductivity type opposite to that of the semiconductor substrate and higher impurity concentration than that of the epitaxial layer.
    Type: Grant
    Filed: March 4, 1981
    Date of Patent: July 2, 1985
    Assignee: Fujitsu Ltd.
    Inventors: Yoshinobu Momma, Yunosuke Kawabe, Osamu Hataishi