Patents by Inventor Yoshinobu Natsui

Yoshinobu Natsui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4800418
    Abstract: A semiconductor integrated circuit of the type having at least one reference element fabricated on a semiconductor chip on which functional elements are formed is obtained by a high integration structure. The reference element is coupled through a switching element to a bonding pad to which a part of the functional elements is connected. The switching element assumes a non-conductive state when the functional elements operate and a conductive state when a voltage applied thereto is outside the normal operating voltage of the functional elements.
    Type: Grant
    Filed: September 6, 1985
    Date of Patent: January 24, 1989
    Assignee: NEC Corporation
    Inventor: Yoshinobu Natsui
  • Patent number: 4719599
    Abstract: A programmable read-only memory device of a junction destruction type is provided with a test circuit for the purpose of detecting a parasitic thyristor effect which may occur in the data programming operation by the user. The test circuit includes first and second additional row lines, a first diode connected between the first additional row line and one column line, a second diode connected between the second additional row line and another column line adjacent to the one column line, and a transistor of a base-open type connected between the second additional row line and the one column line.
    Type: Grant
    Filed: October 30, 1984
    Date of Patent: January 12, 1988
    Assignee: NEC Corporation
    Inventors: Yoshinobu Natsui, Hiroshi Mayumi
  • Patent number: 4347586
    Abstract: A semiconductor programmable memory device fabricated with high integration and programmable with high stability and flexibility is disclosed. The programmable memory device is characterized in that a write current limiter circuit for limiting a write current passing through a programmable element included in the device upon programming or writing within a predetermined value is provided in a current path for feeding the write current.
    Type: Grant
    Filed: June 9, 1980
    Date of Patent: August 31, 1982
    Assignee: Nippon Electric Co., Ltd.
    Inventor: Yoshinobu Natsui
  • Patent number: 4045784
    Abstract: A read only memory integrated circuit includes a first group of transistors serving as the memory elements, and a second group of transistors in a memory peripheral circuit and integrated in the same substrate as the memory transistors. The base width of the first group of memory transistors is greater than that of the second group of transistors in the peripheral circuit.
    Type: Grant
    Filed: January 12, 1976
    Date of Patent: August 30, 1977
    Assignee: Nippon Electric Co., Ltd.
    Inventors: Hiroshi Mayumi, Yoshinobu Natsui, Norio Kusunose