Patents by Inventor Yoshinobu Satou

Yoshinobu Satou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8823106
    Abstract: The present invention mainly provides an ESD protective element which can be built in high voltage semiconductor integrated circuit devices without increasing the chip area. An ESD protective element according to one embodiment has a construction comprising a semiconductor layer, a first region of a first conduction type formed in the semiconductor layer, a first region of a second conduction type formed in the semiconductor layer away from the first region of the first conduction type, a second region of the second conduction type formed in the first region of the second conduction type and has a higher impurity concentration than it, and a second region of the first conduction type formed in the second region of the second conduction type and has a high impurity concentration. The first and second regions of the second conduction type are in an electrically floating state.
    Type: Grant
    Filed: November 8, 2010
    Date of Patent: September 2, 2014
    Assignee: Panasonic Corporation
    Inventors: Teruhisa Ikuta, Yoshinobu Satou
  • Publication number: 20110284956
    Abstract: The semiconductor device comprises a first impurity region having a second conductivity type and formed in a semiconductor layer having a first conductivity type; a body region adjacent to and in contact with the first impurity region and having the first conductivity type; a second impurity region formed in the first impurity region, having the second conductivity type, and having a depth smaller than the first impurity region; a source region formed in the body region and having the second conductivity type; a drain region formed in the second impurity region and having the second conductivity type; and a gate electrode formed via a gate insulating film. In a preferable mode of the semiconductor device, the second impurity region has a higher impurity concentration than the first impurity region and the first impurity region has a depth of 1 ?m or smaller.
    Type: Application
    Filed: May 5, 2011
    Publication date: November 24, 2011
    Inventors: Yoshinobu SATOU, Satoshi Suzuki
  • Publication number: 20110169092
    Abstract: The present invention mainly provides an ESD protective element which can be built in high voltage semiconductor integrated circuit devices without increasing the chip area. An ESD protective element according to one embodiment has a construction comprising a semiconductor layer, a first region of a first conduction type formed in the semiconductor layer, a first region of a second conduction type formed in the semiconductor layer away from the first region of the first conduction type, a second region of the second conduction type formed in the first region of the second conduction type and has a higher impurity concentration than it, and a second region of the first conduction type formed in the second region of the second conduction type and has a high impurity concentration. The first and second regions of the second conduction type are in an electrically floating state.
    Type: Application
    Filed: November 8, 2010
    Publication date: July 14, 2011
    Inventors: Teruhisa IKUTA, Yoshinobu Satou
  • Patent number: 7585708
    Abstract: A thin-film transistor is formed on a transparent substrate and has a gate electrode film layer and a source and drain regions, and further has an alignment mark made of one and the same constituent material as a constituent material of at least one of the gate electrode film layer and source and drain regions and formed at one and the same position as the gate electrode film layer or source and drain region.
    Type: Grant
    Filed: August 30, 2006
    Date of Patent: September 8, 2009
    Assignee: NEC Corporation
    Inventors: Yoshinobu Satou, Katsuhisa Yuda, Hiroshi Tanabe
  • Publication number: 20070045624
    Abstract: A thin-film transistor is formed on a transparent substrate and has a gate electrode film layer and a source and drain regions, and further has an alignment mark made of one and the same constituent material as a constituent material of at least one of the gate electrode film layer and source and drain regions and formed at one and the same position as the gate electrode film layer or source and drain region.
    Type: Application
    Filed: August 30, 2006
    Publication date: March 1, 2007
    Inventors: Yoshinobu Satou, Katsuhisa Yuda, Hiroshi Tanabe
  • Patent number: 7119363
    Abstract: A thin-film transistor is formed on a transparent substrate and has a gate electrode film layer and a source and drain regions, and further has an alignment mark made of one and the same constituent material as a constituent material of at least one of the gate electrode film layer and source and drain regions and formed at one and the same position as the gate electrode film layer or source and drain region.
    Type: Grant
    Filed: August 5, 2004
    Date of Patent: October 10, 2006
    Assignee: NEC Corporation
    Inventors: Yoshinobu Satou, Katsuhisa Yuda, Hiroshi Tanabe
  • Publication number: 20050012098
    Abstract: A thin-film transistor is formed on a transparent substrate and has a gate electrode film layer and a source and drain regions, and further has an alignment mark made of one and the same constituent material as a constituent material of at least one of the gate electrode film layer and source and drain regions and formed at one and the same position as the gate electrode film layer or source and drain region.
    Type: Application
    Filed: August 5, 2004
    Publication date: January 20, 2005
    Inventors: Yoshinobu Satou, Katsuhisa Yuda, Hiroshi Tanabe
  • Patent number: 6822263
    Abstract: A thin-film transistor is formed on a transparent substrate and has a gate electrode film layer and a source and drain regions, and further has an alignment mark made of one and the same constituent material as a constituent material of at least one of the gate electrode film layer and source and drain regions and formed at one and the same position as the gate electrode film layer or source and drain region.
    Type: Grant
    Filed: June 9, 2003
    Date of Patent: November 23, 2004
    Assignee: NEC Corporation
    Inventors: Yoshinobu Satou, Katsuhisa Yuda, Hiroshi Tanabe
  • Publication number: 20030201440
    Abstract: A thin-film transistor is formed on a transparent substrate and has a gate electrode film layer and a source and drain regions, and further has an alignment mark made of one and the same constituent material as a constituent material of at least one of the gate electrode film layer and source and drain regions and formed at one and the same position as the gate electrode film layer or source and drain region.
    Type: Application
    Filed: June 9, 2003
    Publication date: October 30, 2003
    Inventors: Yoshinobu Satou, Katsuhisa Yuda, Hiroshi Tanabe