Patents by Inventor Yoshinobu Takeshita

Yoshinobu Takeshita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240110248
    Abstract: The present disclosure provides a body fluid extract comprising micro RNA.
    Type: Application
    Filed: October 12, 2023
    Publication date: April 4, 2024
    Inventors: Takao Yasui, Daikl TAKESHITA, Yoshinobu BABA
  • Publication number: 20230411513
    Abstract: A semiconductor device including: a first semiconductor layer having a first conductive type; a second semiconductor layer provided on the first semiconductor layer, the second semiconductor layer having a second conductive type that is a conductive type different from the first conductive type; an impurity region of the first conductive type formed at a surface of the second semiconductor layer; first electrodes contacting the impurity region, the second semiconductor layer, and the first semiconductor layer via a first insulating film; and second electrodes contacting the first electrodes via a second insulating film, and contacting the first semiconductor layer via a third insulating film, the second electrodes including PN junctions at borders between upper portions that contact the first semiconductor layer via the third insulating film and lower portions that contact the first semiconductor layer via the third insulating film.
    Type: Application
    Filed: August 8, 2023
    Publication date: December 21, 2023
    Inventors: TOMOMI YAMANOBE, YOSHINOBU TAKESHITA, KAZUTAKA KODAMA, MINAKO ORITU
  • Patent number: 11764294
    Abstract: A semiconductor device including: a first semiconductor layer having a first conductive type; a second semiconductor layer provided on the first semiconductor layer, the second semiconductor layer having a second conductive type that is a conductive type different from the first conductive type; an impurity region of the first conductive type formed at a surface of the second semiconductor layer; first electrodes contacting the impurity region, the second semiconductor layer, and the first semiconductor layer via a first insulating film; and second electrodes contacting the first electrodes via a second insulating film, and contacting the first semiconductor layer via a third insulating film, the second electrodes including PN junctions at borders between upper portions that contact the first semiconductor layer via the third insulating film and lower portions that contact the first semiconductor layer via the third insulating film.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: September 19, 2023
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventors: Tomomi Yamanobe, Yoshinobu Takeshita, Kazutaka Kodama, Minako Oritu
  • Patent number: 10964780
    Abstract: The semiconductor device includes a semiconductor substrate of first conductivity type including a cell area and a peripheral area surrounding cell area on a principal surface thereof, a first diffusion layer which is disposed in peripheral area, surrounds the cell area and has a second conductivity type different from the first conductivity type, an electrode which is disposed in the peripheral area, is in contact with the principal surface through an opening provided in an insulating member and is connected to the first diffusion layer, and a second diffusion layer of the first conductivity type which is formed on the principal surface of a region enclosed in the electrode distant from the first diffusion layer when viewed in a direction perpendicular to the principal surface and includes a linear portion having a first width and a curved portion having a portion with a second width greater than the first width.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: March 30, 2021
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventors: Kenichi Furuta, Toshifumi Kobe, Toshiyuki Orita, Tsuyoshi Inoue, Tomoko Yonekura, Masahiro Haraguchi, Yoshinobu Takeshita, Kiyofumi Kondo
  • Publication number: 20200035783
    Abstract: The semiconductor device includes a semiconductor substrate of first conductivity type including a cell area and a peripheral area surrounding cell area on a principal surface thereof, a first diffusion layer which is disposed in peripheral area, surrounds the cell area and has a second conductivity type different from the first conductivity type, an electrode which is disposed in the peripheral area, is in contact with the principal surface through an opening provided in an insulating member and is connected to the first diffusion layer, and a second diffusion layer of the first conductivity type which is formed on the principal surface of a region enclosed in the electrode distant from the first diffusion layer when viewed in a direction perpendicular to the principal surface and includes a linear portion having a first width and a curved portion having a portion with a second width greater than the first width.
    Type: Application
    Filed: July 19, 2019
    Publication date: January 30, 2020
    Applicant: LAPIS SEMICONDUCTOR CO., LTD
    Inventors: Kenichi Furuta, Toshifumi Kobe, Toshiyuki Orita, Tsuyoshi Inoue, Tomoko Yonekura, Masahiro Haraguchi, Yoshinobu Takeshita, Kiyofumi Kondo
  • Publication number: 20190259873
    Abstract: A semiconductor device including: a first semiconductor layer having a first conductive type; a second semiconductor layer provided on the first semiconductor layer, the second semiconductor layer having a second conductive type that is a conductive type different from the first conductive type; an impurity region of the first conductive type formed at a surface of the second semiconductor layer; first electrodes contacting the impurity region, the second semiconductor layer, and the first semiconductor layer via a first insulating film; and second electrodes contacting the first electrodes via a second insulating film, and contacting the first semiconductor layer via a third insulating film, the second electrodes including PN junctions at borders between upper portions that contact the first semiconductor layer via the third insulating film and lower portions that contact the first semiconductor layer via the third insulating film.
    Type: Application
    Filed: February 20, 2019
    Publication date: August 22, 2019
    Inventors: TOMOMI YAMANOBE, YOSHINOBU TAKESHITA, KAZUTAKA KODAMA, MINAKO ORITU
  • Patent number: 5316610
    Abstract: A depression jig, having a depression chip and a holder for holding the depression chip, is provided which depresses against a wiring substrate a semiconductor chip placed on the wiring substrate. The holder has portions defining penetrations vertically running through the holder. Optical fibers are inserted into the penetrations. A light ray radiates from the optical fiber. The light ray is incident upon the top surface of the depression chip, enters the depression chip, is reflected from a side surface of the depression chip onto the undersurface of the depression chip, and is emitted from the undersurface of the depression chip as an outgoing light ray. A photo-curing resin supplied between the semiconductor chip and the wiring substrate is irradiated with such an outgoing light ray, so that the photo-curing resin hardens.
    Type: Grant
    Filed: December 18, 1992
    Date of Patent: May 31, 1994
    Assignees: Matsushita Electric Industrial Co., Ltd., Matsushita Electronics Corporation
    Inventors: Tomohiro Tamaki, Kenzo Hatada, Hiroaki Fujimoto, Yoshinobu Takeshita
  • Patent number: 5115545
    Abstract: An apparatus for connecting a semiconductor device having multi-electrodes at small pitches to a wiring board in such a manner as to secure the alignment between the electrodes and the wiring patterns, the chips being secured to the wiring board with an insulating resin of a photo-setting nature. The apparatus eliminates the necessity of using heat or supersonic waves, thereby reducing equipment costs.
    Type: Grant
    Filed: March 20, 1990
    Date of Patent: May 26, 1992
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroaki Fujimoto, Kenzo Hatada, Yoshinobu Takeshita, Kazuya Otani, Kimiaki Takeda
  • Patent number: 5037780
    Abstract: A method for fabricating semiconductor devices comprising pressing first and second semiconductor devices against a transparent board at different times by means of first and second pressure tools that are separate from each other and move upward and downward independent of each other so that a difference in thickness between the devices and a deflection of the devices can be absorbed and a reliable electrical connection between the electrodes of the devices and the conductors of the board can be attained, which makes it possible to continuously achieve a highly dense assembly of semiconductor devices with a minute gap therebetween.
    Type: Grant
    Filed: February 1, 1990
    Date of Patent: August 6, 1991
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroaki Fujimoto, Kenzou Hatada, Yoshinobu Takeshita, Kazuya Otani, Koji Hidaka, Tsuguo Sakiyama