Patents by Inventor Yoshinori Fujihashi

Yoshinori Fujihashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6262903
    Abstract: A direct-current power supply circuit, incorporated in an IC card, includes a coil for receiving an amplitude-modulated signal from an external device through electromagnetic induction. A full-wave rectifying circuit rectifies the amplitude-modulated signal received by the coil. The rectified output signal is used to charge a smoothing capacitor. A clamp circuit controls the terminal voltage of the smoothing capacitor to a predetermined level so as to produce a power supply voltage. The clamp circuit controls an output transistor to stabilize the power supply voltage to a constant level. Furthermore, the direct-current power supply circuit includes a short-circuit preventing circuit to forcibly turn off the output transistor when the electric potential difference between both ends of the coil is smaller than a predetermined value, thereby preventing the power supply voltage from suddenly decreasing due to delay of operation of the circuit elements when the coil output becomes zero due to amplitude modulation.
    Type: Grant
    Filed: December 23, 1999
    Date of Patent: July 17, 2001
    Assignee: Denso Corporation
    Inventors: Yoshinori Fujihashi, Tetsuyasu Kitamura, Takuya Harada
  • Patent number: 5789985
    Abstract: A frequency multiplying device which multiplies the frequency of an externally-supplied reference signal PREF includes a digitally-controlled oscillation circuit, which includes a ring oscillator formed of thirty-two inverting circuits in a ring configuration which are adapted to generate sixteen clock signals having a period that is thirty-two times the inversion time of each inverting circuit and a phase interval that is twice the inverting circuit inversion time, and produces an output signal POUT having a period that corresponds to frequency control data CD at a resolution of the phase difference time of the clock signals, a counter/data-latch circuit which counts the clock signal RCK released by the ring oscillator within one period of the reference signal PREF and delivers the frequency control data CD of the count value to the digital oscillation circuit, and a control circuit which controls the operation of the circuits so that the oscillation output signal POUT having the frequency of the reference s
    Type: Grant
    Filed: March 22, 1996
    Date of Patent: August 4, 1998
    Assignee: Nippondenso Co., Ltd.
    Inventors: Shigenori Yamauchi, Takamoto Watanabe, Tadashi Shibata, Yoshinori Fujihashi
  • Patent number: 5708395
    Abstract: A frequency multiplying device which multiplies the frequency of an externally-supplied reference signal PREF includes a digitally-controlled oscillation circuit, which includes a ring oscillator formed of thirty-two inverting circuits in a ring configuration which are adapted to generate sixteen clock signals having a period that is thirty-two times the inversion time of each inverting circuit and a phase interval that is twice the inverting circuit inversion time, and produces an output signal POUT having a period that corresponds to frequency control data CD at a resolution of the phase difference time of the clock signals, a counter/data-latch circuit which counts the clock signal RCK released by the ring oscillator within one period of the reference signal PREF and delivers the frequency control data CD of the count value to the digital oscillation circuit, and a control circuit which controls the operation of the circuits so that the oscillation output signal POUT having the frequency of the reference s
    Type: Grant
    Filed: February 12, 1997
    Date of Patent: January 13, 1998
    Assignee: Nippondenso Co., Ltd.
    Inventors: Shigenori Yamauchi, Takamoto Watanabe, Tadashi Shibata, Yoshinori Fujihashi
  • Patent number: 5408112
    Abstract: A semiconductor strain sensor includes a base, a peripheral section, a central section and a flexible beam. The peripheral section is bent to the base. Bonding strain is generated at a bonding portion between the base and the peripheral section. The central section extends from the peripheral section. The flexible beam extends from the central section and includes a strain detecting element. The strain detecting element changes its electric characteristic when strain is applied thereto. A thickness of the flexible beam is thinner than that of the central section. The bonding strain is transmitted from the bonding portion to the strain detecting element through a transmission path. The transmission path is bent. The bonding strain is attenuated because it is dispersed at a bending portion of the transmission path. The sensor accurately detects the strain to be detected without a bad influence of the bonding strain.
    Type: Grant
    Filed: July 14, 1993
    Date of Patent: April 18, 1995
    Assignee: Nippondenso Co., Ltd.
    Inventors: Akira Tai, Toshitaka Yamada, Yoshinori Fujihashi, Tsuyoshi Fukada, Hirohito Shioya, Yoshimi Yoshino, Hiroshige Sugito
  • Patent number: 4897658
    Abstract: An analog-to-digital converter of the successive-approximation type has a successive-approximation logic circuit for successively generating selection signals defined by significant bits in a digital value, a string of high resistance elements to provide voltage dividers for successively dividing a reference voltage into divided voltages, a switch matrix circuit for generating the divided voltages when activated in response to the selection signals, a comparator for successively comparing an analog level with the divided voltages and for generating comparison signals respectively indicative of the significant bits and an output circuit for generating an output digital signal defined by the significant bits when applied with all the comparison signals, the output circuit being associated with the logic circuit for causing it to generate the selection signals in response to the comparison signals.
    Type: Grant
    Filed: March 18, 1988
    Date of Patent: January 30, 1990
    Assignee: Nippondenso Co., Ltd.
    Inventors: Hiroshi Fujii, Kenji Kanemaru, Yoshinori Fujihashi, Nobuyoshi Morita