Abstract: A semiconductor device includes: a semiconductor region of a first conductivity type having a main surface; a capacitor region of a second conductivity type formed in a surface layer portion of the main surface; and at least one trench structure including a trench formed in the main surface to penetrate the capacitor region, an insulating film covering a wall surface of the trench, and embedded electrodes embedded in the trench so as to form capacitive coupling with the capacitor region through the insulating film.

Abstract: At a position including coordinates of an input start possible point on a first display, an image indicating the input start possible point is displayed, and at a position including coordinates of an input target point on a second display, an image indicating the input target point is displayed. Then, if a coordinate input to the first display includes an input to a position including the coordinates of the input start possible point, and a coordinate input to the second display includes an input to a position including the coordinates of the input target point, based on trajectories of coordinates of the coordinate inputs to the first display and the second display, a positional relationship between the first display and the second display is determined.

Abstract: A semiconductor device includes a semiconductor chip which has a main surface and a main transistor which includes a first system transistor and a second system transistor that are each formed in the main surface so as to be individually controlled, in which the first system transistor includes a first composite cell which is constituted of an ?-number (??2) of first unit transistors that are arrayed so as to be mutually adjacent to the main surface and that each have a first trench structure including a first electrode embedded in a first trench formed in the main surface, and the second system transistor includes a second composite cell which is arranged so as to be adjacent to the first composite cell and constituted of a ?-number (??2) of second unit transistors that are arrayed so as to be mutually adjacent to the main surface and that each have a second trench structure including a second electrode embedded in a second trench formed in the main surface.

Abstract: A semiconductor device includes a main transistor which includes a first system transistor generating a first system current and a second system transistor generating a second system current independently of the first system transistor and which generates an output current including the first system current and the second system current, a first system monitor transistor which generates a first system monitor current that corresponds to the first system current, and a second system monitor transistor which generates a second system monitor current that corresponds to the second system current.

Abstract: A semiconductor device includes: a semiconductor layer having a partitioned region partitioned by a trench; a field insulating layer which is formed on a main surface of the semiconductor layer at an interval from the trench toward an inner side of the partitioned region and covers the partitioned region; a trench insulating layer formed at least in the trench; an intermediate region annularly formed between the field insulating layer on the main surface of the semiconductor layer and the trench insulating layer; and a bridge insulating layer which is formed in the intermediate region and connects the field insulating layer and the trench insulating layer, wherein the bridge insulating layer has a bridge buried portion buried in the main surface of the semiconductor layer.

Abstract: A semiconductor device includes a substrate having a main surface, and a temperature-sensitive diode structure having a trench formed in the main surface, a polysilicon layer embedded in the trench, a p-type anode region formed in the polysilicon layer, and an n-type cathode region formed in the polysilicon layer.

Abstract: A semiconductor device includes a semiconductor layer, an insulation gate-type first transistor which is formed in the semiconductor layer, an insulation gate-type second transistor which is formed in the semiconductor layer, and a control wiring which is formed on the semiconductor layer such as to be electrically connected to the first transistor and the second transistor, and transmits control signals that control the first transistor and the second transistor to be in ON states in a normal operation and that control the first transistor to be in an OFF state and the second transistor to be in an ON state in an active clamp operation.

Abstract: A semiconductor device includes a semiconductor chip, and an n-system gate divided transistor, where the “n” is not less than 2, that includes n-number of system transistors formed in the semiconductor chip such as to be individually controlled and that is configured such as to generate a single output signal by selective controls of the n-number of system transistors.

Abstract: A semiconductor device includes a substrate having a main surface, and a temperature-sensitive diode structure having a trench formed in the main surface, a polysilicon layer embedded in the trench, a p-type anode region formed in the polysilicon layer, and an n-type cathode region formed in the polysilicon layer.

Abstract: A semiconductor device includes a semiconductor layer that has a main surface including a defined region defined by a trench, a trench insulation layer formed in the trench, a field insulation layer that covers the defined region away from the trench, and a bridge insulation layer that is formed in a region between the trench and the field insulation layer in the defined region and that is connected to the trench insulation layer and to the field insulation layer.

Abstract: A semiconductor device includes a semiconductor layer that has a main surface including a defined region defined by a trench, a trench insulation layer formed in the trench, a field insulation layer that covers the defined region away from the trench, and a bridge insulation layer that is formed in a region between the trench and the field insulation layer in the defined region and that is connected to the trench insulation layer and to the field insulation layer.

Abstract: A method for manufacturing an image display element including: a front panel; a back panel facing the front panel; plural pixels arranged in a matrix between the panels, and to be selected to be in a display or non-display state; and plural electrodes for controlling the pixels, the panels being bonded with the pixels and the electrodes interposed therebetween, and the electrodes being connected to a driving control circuit via metal wires, includes a first step of performing dicing from the back side of the opposing surface from the front panel, and forming a groove part such that electrode terminals connected to the electrodes are exposed between adjacent plural pixel lines, with the back panel bonded thereto, and a second step of forming the metal wires so as to be connected to the electrode terminals exposed at the groove part.

Abstract: An image display element includes: a front panel; a back panel opposite thereto; a plurality of pixels arranged between both the panels; and plural electrodes for controlling the pixels. The panels are bonded with the pixels and the electrodes interposed therebetween, and the electrodes are connected to a driving circuit via metal film wires. The back panel is divided so as to expose electrode terminals, and a groove part V-shaped in cross section is formed at the divided portion. The metal film wires are formed on the top surface of the back panel, and the electrode terminals and the metal film wires are connected by a conductive paste coated along the tilt surfaces forming the groove part. Partitions are disposed between the adjacent electrode terminals at the bottom of the groove part.

Abstract: An image display element includes: a front panel; a back panel opposite to the front panel; a plurality of pixels arranged in a matrix between both the panels, and to be selected to be in a display or non-display state; and plural electrodes for controlling the pixels. Both the panels are bonded together with the pixels and the electrodes interposed therebetween, and the electrodes are connected to a driving control circuit via metal wires. The back panel is divided such that electrode terminals connected to the electrodes are exposed between adjacent plural pixel lines, and a groove part having a shape wider at the top on the back side of the opposing surface from the front panel than at the bottom is formed at the divided portion. The metal wires are connected to the exposed electrode terminals of the groove part.

Abstract: An image display element includes: a front panel; a back panel opposite thereto; a plurality of pixels arranged in a matrix between both the panels; and plural electrodes for controlling the pixels. Both the panels are bonded together with the pixels and the electrodes interposed therebetween, and the electrodes are connected to a driving circuit via metal film wires. Division is performed so as to expose electrode terminals, and a groove part V-shaped in cross section is formed at the divided portion. The metal film wires are formed on the surface of the top of the back panel, and the electrode terminals and the metal film wires are connected by a conductive paste coated along the tilt surfaces forming the groove part.

Abstract: A method for manufacturing an image display element including: a front panel; a back panel facing the front panel; plural pixels arranged in a matrix between the panels, and to be selected to be in a display or non-display state; and plural electrodes for controlling the pixels, the panels being bonded with the pixels and the electrodes interposed therebetween, and the electrodes being connected to a driving control circuit via metal wires, includes a first step of performing dicing from the back side of the opposing surface from the front panel, and forming a groove part such that electrode terminals connected to the electrodes are exposed between adjacent plural pixel lines, with the back panel bonded thereto, and a second step of forming the metal wires so as to be connected to the electrode terminals exposed at the groove part.

Abstract: A method for manufacturing an image display element including: a front panel; a back panel facing the front panel; plural pixels arranged in a matrix between the panels, and to be selected to be in a display or non-display state; and plural electrodes for controlling the pixels, the panels being bonded with the pixels and the electrodes interposed therebetween, and the electrodes being connected to a driving control circuit via metal wires, includes a first step of performing dicing from the back side of the opposing surface from the front panel, and forming a groove part such that electrode terminals connected to the electrodes are exposed between adjacent plural pixel lines, with the back panel bonded thereto, and a second step of forming the metal wires so as to be connected to the electrode terminals exposed at the groove part.

Abstract: An image display element includes: a front panel; a back panel opposite thereto; plural pixels arranged in a matrix between the panels; and plural electrodes for controlling the pixels. The panels are bonded with the pixels and the electrodes interposed therebetween. The electrodes are connected to a driving circuit via metal film wires. The back panel is divided so as to expose electrode terminals, and a groove part V-shaped in cross section is formed at the divided portion. The metal film wires are formed on the top surface of the back panel, and the electrode terminals and the metal film wires are connected by a conductive paste coated along the tilt surfaces forming the groove part. A contact resistance reducing means is disposed at the connection part interface between the electrode terminal and the conductive paste.

Abstract: The present invention is a planar antenna member configured to introduce electromagnetic waves generated by an electromagnetic-wave generating source into a processing vessel of a plasma processing apparatus, the planar antenna member comprising: a base member of a circular plate shape, made of a conductive material; and a plurality of through-holes formed in the base member of a circular plate shape, the through-holes being configured to radiate the electromagnetic waves; wherein: the through-holes include a plurality of first through-holes which are arranged on a circumference of a circle whose center corresponds to a center of the planar antenna member, and a plurality of second through-holes which are arranged concentrically with the circle outside the first through-holes; a ratio L1/r is within a range between 0.35 and 0.

Abstract: In a plasma oxidation processing apparatus (100) which supplies a high-frequency bias power to an electrode (7) embedded in a stage (5), the interior surface, which is to be exposed to a plasma, of an aluminum lid (27) which functions as an opposite electrode for the stage (5) is coated with a silicon film (48) as a protective film. Positioned adjacent to the silicon film (48), an upper liner (49a) and a thicker lower liner (49b) are provided on the interior surfaces of a second container (3) and a first container (2). This prevents a short circuit or abnormal electrical discharge to the interior surfaces, making it possible to form a proper high-frequency current path and enhance the efficiency of power consumption.