Patents by Inventor Yoshinori Hayamizu
Yoshinori Hayamizu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8492879Abstract: On a surface of a semiconductor substrate, a plurality of terraces formed stepwise by an atomic step are formed in the substantially same direction. Using the semiconductor substrate, a MOS transistor is formed so that no step exists in a carrier traveling direction (source-drain direction).Type: GrantFiled: October 6, 2008Date of Patent: July 23, 2013Assignees: National University Corporation Tohoku University, Shin-Etsu Handotai Co., Ltd.Inventors: Tadahiro Ohmi, Akinobu Teramoto, Tomoyuki Suwa, Rihito Kuroda, Hideo Kudo, Yoshinori Hayamizu
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Patent number: 8187954Abstract: The present invention provides a method for manufacturing a silicon single crystal wafer, in which a silicon single crystal wafer that is fabricated based on a Czochralski method and has an entire plane in a radial direction formed of an N region is subjected to a rapid thermal annealing in an oxidizing atmosphere, an oxide film formed in the rapid thermal annealing in the oxidizing atmosphere is removed, and then a rapid thermal annealing is carried out in a nitriding atmosphere, an Ar atmosphere, or a mixed atmosphere of these atmospheres. As a result, there can be provided the manufacturing method that can inexpensively manufacture a silicon single crystal wafer both in which a DZ layer is formed in a wafer surface layer to provide excellent device characteristics and in which an oxide precipitate functioning as a gettering site can be sufficiently formed in a bulk region.Type: GrantFiled: January 24, 2008Date of Patent: May 29, 2012Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Yoshinori Hayamizu, Hiroyasu Kikuchi
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Publication number: 20120001301Abstract: An annealed wafer obtained by performing rapid thermal annealing on a silicon single crystal wafer sliced from a silicon single crystal ingot in which an entire plane is an OSF region, an N region outside an OSF region, or a mixed region thereof, the silicon single crystal ingot being grown by the Czochralski method, in which RIE defects do not exist in a region having at least a depth of 1 ?m from a surface, a good chip yield of a TDDB characteristic is 80% or more, and a depth of a region where an oxygen concentration is decreased due to outward diffusion is within 3 ?m from the surface, and a method for producing an annealed wafer.Type: ApplicationFiled: March 17, 2010Publication date: January 5, 2012Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Koji Ebara, Yoshinori Hayamizu, Hiroyasu Kikuchi
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Publication number: 20100213516Abstract: On a surface of a semiconductor substrate, a plurality of terraces formed stepwise by an atomic step are formed in the substantially same direction. Using the semiconductor substrate, a MOS transistor is formed so that no step exists in a carrier traveling direction (source-drain direction).Type: ApplicationFiled: October 6, 2008Publication date: August 26, 2010Inventors: Tadahiro Ohmi, Akinobu Teramoto, Tomoyuki Suwa, Rihito Kuroda, Hideo Kudo, Yoshinori Hayamizu
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Publication number: 20100105191Abstract: The present invention provides a method for manufacturing a silicon single crystal wafer, in which a silicon single crystal wafer that is fabricated based on a Czochralski method and has an entire plane in a radial direction formed of an N region is subjected to a rapid thermal annealing in an oxidizing atmosphere, an oxide film formed in the rapid thermal annealing in the oxidizing atmosphere is removed, and then a rapid thermal annealing is carried out in a nitriding atmosphere, an Ar atmosphere, or a mixed atmosphere of these atmospheres. As a result, there can be provided the manufacturing method that can inexpensively manufacture a silicon single crystal wafer both in which a DZ layer is formed in a wafer surface layer to provide excellent device characteristics and in which an oxide precipitate functioning as a gettering site can be sufficiently formed in a bulk region.Type: ApplicationFiled: January 24, 2008Publication date: April 29, 2010Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Yoshinori Hayamizu, Hiroyasu Kikuchi
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Patent number: 7081422Abstract: There are provided a heat-treating method capable of suppressing generation of slip in a CZ silicon single crystal wafer having a diameter of mainly 300 mm or more even under high temperature heat treatment to annihilate grown-in defects in the vicinity of a surface of the wafer, and an annealed wafer having a DZ layer in a surface layer of the wafer and oxide precipitates in the bulk thereof at a high density which exert a high gettering effect. First heat treatment of a silicon single crystal wafer manufactured from a silicon single crystal ingot pulled by means of a Czochralski method is performed at a temperature in the range of 600 to 1100° C. to form oxide precipitates in the bulk of the wafer, and thereafter, second heat treatment is performed at a temperature in the range of 1150 to 1300° C.Type: GrantFiled: December 11, 2001Date of Patent: July 25, 2006Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Yoshinori Hayamizu, Satoshi Tobe, Norihiro Kobayashi
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Publication number: 20060121291Abstract: There are provided a heat-treating method capable of suppressing generation of slip in a CZ silicon single crystal wafer having a diameter of mainly 300 mm or more even under high temperature heat treatment to annihilate grown-in defects in the vicinity of a surface of the wafer, and an annealed wafer having a DZ layer in a surface layer of the wafer and oxide precipitates in the bulk thereof at a high density which exert a high gettering effect. First heat treatment of a silicon single crystal wafer manufactured from a silicon single crystal ingot pulled by means of a Czochralski method is performed at a temperature in the range of 600 to 1100° C. to form oxide precipitates in the bulk of the wafer, and thereafter, second heat treatment is performed at a temperature in the range of 1150 to 1300° C.Type: ApplicationFiled: November 3, 2005Publication date: June 8, 2006Inventors: Yoshinori Hayamizu, Satoshi Tobe, Norihiro Kobayashi
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Patent number: 6858094Abstract: The present invention provides a silicon wafer having a DZ layer near a surface and an oxide precipitate layer in a bulk portion, wherein interstitial oxygen concentrations of the DZ layer, the oxide precipitate layer and a transition region between the DZ layer and the oxide precipitate layer are all 8 ppma or less, and an epitaxial silicon wafer, wherein an epitaxial layer is formed on a surface of the silicon wafer, as well as a method for producing a silicon wafer, which comprises growing a silicon single crystal ingot having an initial interstitial oxygen concentration of 10 to 25 ppma by the Czochralski method, processing the silicon single crystal ingot into a wafer, and subjecting the wafer to a first heat treatment at 950 to 1050° C. for 2 to 5 hours, a second heat treatment at 450 to 550° C. for 4 to 10 hours, a third heat treatment at 750 to 850° C. for 2 to 8 hours, and a fourth heat treatment at 950 to 1100° C. for 8 to 24 hours.Type: GrantFiled: September 14, 2001Date of Patent: February 22, 2005Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Wei Feig Qu, Yoshinori Hayamizu, Hiroshi Takeno
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Patent number: 6548035Abstract: A silicon single crystal wafer for epitaxial growth grown by the CZ method, which is doped with nitrogen and has a V-rich region over its entire plane, or doped with nitrogen, has an OSF region in its plane, and shows an LEP density of 20/cm2 or less or an OSF density of 1×104/cm2 or less in the OSF region, epitaxial wafer utilizing the substrate, as well as methods for producing them and method for evaluating a substrate suitable for an epitaxial wafer. There are provided a substrate for an epitaxial wafer that suppresses crystal defects to be generated in an epitaxial layer when epitaxial growth is performed on a CZ silicon single crystal wafer doped with nitrogen and also has superior IG ability, epitaxial wafer utilizing the substrate, as well as methods for producing them and method for evaluating a substrate suitable for an epitaxial wafer.Type: GrantFiled: June 14, 2001Date of Patent: April 15, 2003Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Akihiro Kimura, Makoto Iida, Yoshinori Hayamizu, Ken Aihara, Masanori Kimura
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Patent number: 6544332Abstract: A method for producing a silicon single crystal in accordance with CZ method, characterized in that before producing the crystal having a predetermined kind and concentration of impurity, another silicon single crystal having the same kind and concentration of impurity as the crystal to be produced is grown to thereby determine an agglomeration temperature zone of grown-in defects thereof, and then based on the temperature, growth condition of the crystal to be produced or temperature distribution within a furnace of a pulling apparatus is set such that a cooling rate of the crystal for passing through the agglomeration temperature zone is a desired rate to thereby produce the silicon single crystal. A silicon single crystal produced in accordance with the above method, characterized in that a density of LSTD before subjecting to heat treatment is 500 number/cm2 or more and the average defect size is 70 nm or less.Type: GrantFiled: April 26, 2001Date of Patent: April 8, 2003Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Makoto Iida, Masanori Kimura, Hiroshi Takeno, Yoshinori Hayamizu
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Patent number: 6544656Abstract: A silicon wafer is produced by growing a silicon single crystal ingot having a resistivity of 100 &OHgr;·cm or more and an initial interstitial oxygen concentration of 10 to 25 ppma by the Czochralski method, processing the silicon single crystal ingot into a wafer, and subjecting the wafer to an oxygen precipitation heat treatment so that a residual interstitial oxygen concentration in the wafer should become 8 ppma or less. A silicon wafer produced as described above shows little decrease in resistivity even after a heat treatment in device production etc. Further, if a silicon wafer is produced and heat-treated so that the wafer should have the above-defined initial interstitial oxygen concentration and residual interstitial oxygen concentration, slip dislocations in a subsequent heat treatment process are prevented irrespective of resistivity.Type: GrantFiled: November 7, 2000Date of Patent: April 8, 2003Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Takao Abe, Ken Aihara, Shoji Akiyama, Tetsuya Igarashi, Weifeng Qu, Yoshinori Hayamizu, Shigeru Saito
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Publication number: 20030013321Abstract: There are provided a heat-treating method capable of suppressing generation of slip in a CZ silicon single crystal wafer having a diameter of mainly 300 mm or more even under high temperature heat treatment to annihilate grown-in defects in the vicinity of a surface of the wafer, and an annealed wafer having a DZ layer in a surface layer of the wafer and oxide precipitates in the bulk thereof at a high density which exert a high gettering effect. First heat treatment of a silicon single crystal wafer manufactured from a silicon single crystal ingot pulled by means of a Czochralski method is performed at a temperature in the range of 600 to 1100° C. to form oxide precipitates in the bulk of the wafer, and thereafter, second heat treatment is performed at a temperature in the range of 1150 to 1300° C.Type: ApplicationFiled: August 28, 2002Publication date: January 16, 2003Inventors: Yoshinori Hayamizu, Satoshi Tobe, Norihiro Kobayashi
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Patent number: 6478883Abstract: A silicon wafer for epitaxial growth consisting of a highly boron-doped silicon single crystal wafer, an antimony-doped silicon single crystal wafer or a phosphorus-doped silicon single crystal wafer, which allows easy oxygen precipitation and exhibits high gettering ability in spite of its suppressed oxygen concentration, and an epitaxial silicon wafer in which an epitaxial layer grown by using the aforementioned wafer as a substrate wafer has an extremely low heavy metal impurity concentration are produced with high productivity and supplied. The present invention relates to a boron-doped silicon single crystal wafer having a resistivity of from 10 m&OHgr;·cm to 100 m&OHgr;·cm, an antimony-doped silicon single crystal wafer, or a phosphorus-doped silicon single crystal wafer, which are produced by slicing a silicon single crystal ingot grown by the Czochralski method with nitrogen doping.Type: GrantFiled: April 18, 2000Date of Patent: November 12, 2002Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Masaro Tamatsuka, Ken Aihara, Katsuhiko Miki, Hiroshi Takeno, Yoshinori Hayamizu
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Patent number: 6277715Abstract: Provided is a production method for a silicon epitaxial wafer having an internal gettering (IG) capability at a level equal to that of a CZ silicon mirror-finished wafer. In the production method for a silicon epitaxial wafer in which silicon single crystal is epitaxially grown on a silicon wafer; a heat treatment of the silicon wafer is performed at a temperature within ±50° C. of a holding temperature for the first stage heat treatment which is to be firstly effected as a heat treatment in the device fabrication process after the epitaxial growth process for a time period equal to or more than a time period in which a precipitate nucleus from interstitial oxygen in the silicon wafer can grow to a size which survives through the epitaxial growth process, prior to the epitaxial growth process, and thereafter, the epitaxial growth is effected; or a heat treatment of the silicon wafer is performed being kept at a temperature within ±50° C.Type: GrantFiled: May 28, 1999Date of Patent: August 21, 2001Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Hiroshi Takeno, Yoshinori Hayamizu
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Patent number: 6140131Abstract: The present invention is to provide a method and apparatus for detecting heavy metals within the bulk of a silicon wafer with high sensitivity. An electric field is applied to a surface of the silicon wafer in order to aggregate heavy metals existing within the bulk of the silicon wafer to the surface of the wafer or the vicinity thereof, and the heavy metals aggregated to the surface of the wafer or the vicinity of the surface are analyzed. The application of an electric field is performed through corona-discharge treatment of the surface of the wafer, or through application of voltage to the surface of the wafer via a contact or non-contact electrode. Alternatively, an x-ray beam is radiated onto the surface of the silicon wafer in order to aggregate heavy metals existing within the bulk of the silicon wafer to the surface of the wafer or the vicinity thereof, and the heavy metals aggregated to the surface of the wafer or the vicinity thereof are analyzed.Type: GrantFiled: September 24, 1998Date of Patent: October 31, 2000Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Ken Sunakawa, Kiichiro Asako, Toko Yagi, Yoshinori Hayamizu
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Patent number: 5916824Abstract: A silicon wafer is held in an airtight chamber by a silicon wafer holder. The silicon wafer holder is cooled by a cooler. High purity nitric acid is stored in a storage container disposed in the airtight container. The storage container is heated by a heater, thereby producing nitric acid gas. The nitric acid gas is condensed on the surface of the silicon wafer so that a thin film is formed. Thus, the surface of the silicon wafer is rendered hydrophilic. Thereafter, high purity hydrofluoric acid is dropped on high purity nitric acid in the storage container by an acid dropper, thereby producing hydrofluoric acid gas. By introducing the hydrofluoric acid gas into the thin film formed on the surface of the silicon wafer, an etching is performed while maintaining the surface of the silicon wafer in a good condition.Type: GrantFiled: May 30, 1996Date of Patent: June 29, 1999Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Masanori Mayuzumi, Katsuaki Yoshizawa, Yoshinori Hayamizu