Abstract: A method for forming a multilayer conductive structure includes forming a first conductive portion; forming a second conductive portion containing ruthenium (Ru) therein on the first conductive portion; forming a third conductive portion on the second conductive portion; and performing a silicidation process on the second conductive portion.

Abstract: A method for forming a multilayer conductive structure includes forming a first conductive portion; forming a second conductive portion containing ruthenium (Ru) therein on the first conductive portion; forming a third conductive portion on the second conductive portion; and performing a silicidation process on the second conductive portion.

Abstract: One method for manufacturing a semiconductor device includes: forming provisional active regions that are shaped such that active regions that are adjacent in an X direction are connected to each other, forming a sacrificial film, performing etching, including the sacrificial film, so as to form a plurality of first trenches that separate the active regions, embedding element-isolating insulating films in the first trenches and then removing the sacrificial film, forming first side-wall insulating films that cover the exposed side surfaces of the element-isolating insulating films and second side-wall insulating films that cover the side surfaces of the first side-wall insulating films, embedding cap insulating films in second trenches that appear due to the formation of the second side-wall insulating films, and forming a plurality of third trenches at the positions of the second side-wall insulating films and forming word lines thereunder.

Abstract: One method for manufacturing a semiconductor device includes: forming provisional active regions that are shaped such that active regions that are adjacent in an X direction are connected to each other, forming a sacrificial film, performing etching, including the sacrificial film, so as to form a plurality of first trenches that separate the active regions, embedding element-isolating insulating films in the first trenches and then removing the sacrificial film, forming first side-wall insulating films that cover the exposed side surfaces of the element-isolating insulating films and second side-wall insulating films that cover the side surfaces of the first side-wall insulating films, embedding cap insulating films in second trenches that appear due to the formation of the second side-wall insulating films, and forming a plurality of third trenches at the positions of the second side-wall insulating films and forming word lines thereunder.

Abstract: One method for manufacturing a semiconductor device includes: forming provisional active regions that are shaped such that active regions that are adjacent in an X direction are connected to each other, forming a sacrificial film, performing etching, including the sacrificial film, so as to form a plurality of first trenches that separate the active regions, embedding element-isolating insulating films in the first trenches and then removing the sacrificial film, forming first side-wall insulating films that cover the exposed side surfaces of the element-isolating insulating films and second side-wall insulating films that cover the side surfaces of the first side-wall insulating films, embedding cap insulating films in second trenches that appear due to the formation of the second side-wall insulating films, and forming a plurality of third trenches at the positions of the second side-wall insulating films and forming word lines thereunder.

Abstract: Provided is a semiconductor device in which a voltage does not need to be applied to an element-isolating region that self-aligns with word lines (WL).

Abstract: A semiconductor device includes a semiconductor substrate, a first insulating film on the semiconductor substrate, a first electrode film on the first insulating film, a second insulating film on the first electrode film, a second electrode film on the second insulating film, an opening extending through the second electrode film and the second insulating film and into the first electrode film, a barrier film over the surfaces of the opening and a portion of the first electrode film exposed within the opening, and a metal film disposed on the barrier film disposed over the surfaces of the opening. The barrier film directly contacts at least a portion of the second insulating film exposed in the opening and the metal film overlies the location where the barrier film directly contacts the second insulating film exposed in the opening.

Abstract: Disclosed herein is a device that includes: a semiconductor substrate; a first semiconductor pillar having a side surface that is substantially perpendicular to a main surface of the semiconductor substrate; an insulator pillar having a side surface that is substantially perpendicular to the main surface of the semiconductor substrate and a top surface that is substantially parallel to the main surface of the semiconductor substrate; a first gate electrode covering the side surface of the first semiconductor pillar with intervention of a first gate insulation film; an extended gate electrode covering the side surface of the insulator pillar, the extended gate electrode being configured integrally with the first gate electrode; and a conductive film formed on the top surface of the insulator pillar, the conductive film being in contact with the extended gate electrode in a position above the top surface of the insulator pillar.

Abstract: A semiconductor device includes a substrate having a groove in a periphery, a gate electrode partially embedded in the groove to sandwich the substrate from opposite directions by side walls of the groove, and a diffusion layer formed over the substrate and surrounded by the gate electrode. A resistance value of the diffusion layer is changed by changing a potential between the gate electrode and the diffusion layer.

Abstract: The present invention provides a semiconductor device having a plurality of vertical transistors, which includes, on a substrate, a semiconductor pillar 5; gate electrode 11 provided on the side of the pillar via gate insulating film 10; first diffusion layer 9 connected to the bottom of the pillar; and second diffusion layer 16 connected to the top of the pillar, second diffusion layer 16 includes first portion 14 formed within the area over the pillar, and second portion 15 which is an epitaxial growth layer, formed on the first portion and contacting with insulating film 17 which is provided between adjacent vertical transistors.

Abstract: To provide a semiconductor device including a first silicon pillar, an interlayer dielectric film provided on an upper surface of the first silicon pillar and having a through-hole filled with a conductive material, and a first-diffusion-layer contact plug provided on an upper-side opening of the through-hole. An area of a lower-side opening of the through-hole is equal to an area of the upper surface of the first silicon pillar, and an area of the upper-side opening of the through-hole is larger than the area of the lower-side opening of the through-hole. With this configuration, an area of a contact surface between the conductive material within the through-hole and the first-diffusion-layer contact plug is larger than the area of the upper surface of the first silicon pillar.

Abstract: A semiconductor device may include, but is not limited to, a transistor and a contact plug pillar of an impurity-diffused semiconductor. The transistor includes a semiconductor channel pillar having a vertical channel; and a first diffusion region adjacent to a lower portion of the semiconductor channel pillar. The contact plug pillar of an impurity-diffused semiconductor is coupled to the first diffusion region.

Abstract: The present invention provides a semiconductor device having a plurality of vertical transistors, which includes, on a substrate, a semiconductor pillar 5; gate electrode 11 provided on the side of the pillar via gate insulating film 10; first diffusion layer 9 connected to the bottom of the pillar; and second diffusion layer 16 connected to the top of the pillar, second diffusion layer 16 includes first portion 14 formed within the area over the pillar, and second portion 15 which is an epitaxial growth layer, formed on the first portion and contacting with insulating film 17 which is provided between adjacent vertical transistors.

Abstract: A semiconductor device includes: a semiconductor substrate; a silicon pillar having a side surface perpendicular to a main surface of the semiconductor substrate; a gate dielectric film that covers a side surface of the silicon pillar; a gate electrode that has an inner-circumference side surface and an outer-circumference side surface which are perpendicular to the main surface of the semiconductor substrate, and covers a side surface of the silicon pillar such that the inner-circumference side surface and the side surface of the silicon pillar face each other via the gate dielectric film; a gate-electrode protection film that covers at least a part of the outer-circumference side surface of the gate electrode; an interlayer dielectric film provided above the gate electrode and the gate-electrode protection film; and a gate contact plug that is embedded in a contact hole provided on the interlayer dielectric film and is in contact with the gate electrode and the gate-electrode protection film.

Abstract: To provide a semiconductor device including a first silicon pillar, an interlayer dielectric film provided on an upper surface of the first silicon pillar and having a through-hole filled with a conductive material, and a first-diffusion-layer contact plug provided on an upper-side opening of the through-hole. An area of a lower-side opening of the through-hole is equal to an area of the upper surface of the first silicon pillar, and an area of the upper-side opening of the through-hole is larger than the area of the lower-side opening of the through-hole. With this configuration, an area of a contact surface between the conductive material within the through-hole and the first-diffusion-layer contact plug is larger than the area of the upper surface of the first silicon pillar.

Abstract: There is provided a semiconductor device in which an upper main electrode region of a 3D pillar SGT includes a selective epitaxial growth semiconductor film, at least two adjacent 3D pillar SGTs are interconnected in parallel with each other by joining the selective epitaxial growth semiconductor films together, thereby the need for providing an interconnect layer for interconnecting 3D pillar SGTs in parallel with each other is eliminated.

Abstract: A semiconductor device includes a first semiconductor pillar, a first gate insulating film, a gate electrode, and a first contact. The first semiconductor pillar extends upwardly from a semiconductor substrate. The first gate insulating film covers side surfaces of the first semiconductor pillar. The gate electrode covers the first gate insulating film. The first gate insulating film insulates the gate electrode from the first semiconductor pillar. The first contact partially overlaps, in plane view, the first semiconductor pillar and the gate electrode. The first contact includes a silicon layer having a top level which is higher than a top level of the gate electrode.

Abstract: The present invention has an object to provide a method for manufacturing a dynamic random access memory capable of reducing a defect rate even if the memory has a large packing density. The method of the present invention is a method for manufacturing a dynamic random access memory having memory array areas and a peripheral circuit area arranged in a semiconductor substrate and a silicon nitride film provided over the memory array areas and the peripheral circuit area, the method having at least a step (1) of eliminating the silicon nitride film provided in the peripheral circuit area; and a step (2) of processing in an atmosphere of a hydrogen gas a substrate-to-be-processed obtained by the step (1).

Abstract: The present invention has an object to provide a method for manufacturing a dynamic random access memory capable of reducing a defect rate even if the memory has a large packing density. The method of the present invention is a method for manufacturing a dynamic random access memory having memory array areas and a peripheral circuit area arranged in a semiconductor substrate and a silicon nitride film provided over the memory array areas and the peripheral circuit area, the method having at least a step (1) of eliminating the silicon nitride film provided in the peripheral circuit area; and a step (2) of processing in an atmosphere of a hydrogen gas a substrate-to-be-processed obtained by the step (1).