Patents by Inventor Yoshinori Kitamura

Yoshinori Kitamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090241588
    Abstract: A component mounting plate (s1) of a casing for a refrigeration system includes an inner sub-plate (2), an outer sub-plate (3) and a heat insulating layer (4) filled with a heat insulating material, such as urethane. The inner sub-plate (2) is formed with a mounting hole (31) through which a mounting bolt (30) for mounting a component (16) to the inner sub-plate (2) passes. The heat insulating layer (4) contains a nut (40) disposed to correspond to the mounting hole (31) and an L-piece (41) disposed to correspond to the mounting hole (31) and including an extension (43) and a seat (42) with the nut (40) welded thereto. The L-piece is disposed in the heat insulating layer (4) with the seat (42) in contact with the inner sub-plate (2) and the extension (43) extending towards the outer sub-plate (3).
    Type: Application
    Filed: September 29, 2006
    Publication date: October 1, 2009
    Inventors: Yoshinori Kitamura, Hiroki Ishihara
  • Publication number: 20090133420
    Abstract: A casing (11) for use in a freezing container is provided with a through hole (H) for insertion of the piping of a refrigerant circuit therethrough. Each opening end of the through hole (H) is covered over with a respective mesh sheet (31, 32). With each opening end of the through hole (H) covered over with the mesh sheet (31, 32), the tip end of a filling nozzle (33) is inserted until it reaches the middle of the through hole (H) and a sealant material is injected. The injected sealant material is held back within the through hole (H) by each mesh sheet (31, 32) and, with the progress of the injection of the sealant material, the air present in the through hole (H) is purged out through each mesh sheet (31, 32).
    Type: Application
    Filed: September 13, 2006
    Publication date: May 28, 2009
    Inventors: Yoshinori Kitamura, Mitsuhiro Oshitani
  • Patent number: 7462531
    Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate including first and second element-formation regions partitioned by an isolation trench, first and second lower gate insulating films formed on the first and second element-formation regions, first and second floating gates formed on the first and second lower gate insulating films, an isolation insulating film formed at least in the isolation trench and has a depression formed in an upper surface thereof, an upper gate insulating film formed on the first and second floating gates, and a control gate line including an opposed portion opposed to the first and second floating gates, with the upper gate insulating film being interposed, and a portion located inside the depression, the first floating gate including a side surface opposed to the second floating gate and entirely aligns with a side surface included in the first element-formation region and defined by the isolation trench.
    Type: Grant
    Filed: March 1, 2007
    Date of Patent: December 9, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshinori Kitamura, Shigeki Sugimoto
  • Publication number: 20080251883
    Abstract: A semiconductor device includes a semiconductor substrate formed with a plurality of first element isolation trenches having respective first opening widths and a plurality of second element isolation trenches having larger opening widths than the first opening widths, element isolation insulating films buried in the first element isolation trenches so that upper parts of the trenches have partial openings, respectively and buried in the second element isolation trenches respectively, and coating type oxide films formed so as to fill the openings of the first element isolation trenches, respectively.
    Type: Application
    Filed: June 20, 2008
    Publication date: October 16, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshinori KITAMURA, Koichi Matsuno, Kazunori Nishikawa
  • Publication number: 20080206976
    Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate including first and second element-formation regions partitioned by an isolation trench, first and second lower gate insulating films formed on the first and second element-formation regions, first and second floating gates formed on the first and second lower gate insulating films, an isolation insulating film formed at least in the isolation trench and has a depression formed in an upper surface thereof, an upper gate insulating film formed on the first and second floating gates, and a control gate line including an opposed portion opposed to the first and second floating gates, with the upper gate insulating film being interposed, and a portion located inside the depression, the first floating gate including a side surface opposed to the second floating gate and entirely aligns with a side surface included in the first element-formation region and defined by the isolation trench.
    Type: Application
    Filed: April 18, 2008
    Publication date: August 28, 2008
    Inventors: Yoshinori KITAMURA, Shigeki SUGIMOTO
  • Patent number: 7402499
    Abstract: A semiconductor device includes a semiconductor substrate formed with a plurality of first element isolation trenches having respective first opening widths and a plurality of second element isolation trenches having larger opening widths than the first opening widths, element isolation insulating films buried in the first element isolation trenches so that upper parts of the trenches have partial openings, respectively and buried in the second element isolation trenches respectively, and coating type oxide films formed so as to fill the openings of the first element isolation trenches, respectively.
    Type: Grant
    Filed: June 2, 2006
    Date of Patent: July 22, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshinori Kitamura, Koichi Matsuno, Kazunori Nishikawa
  • Publication number: 20070155088
    Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate including first and second element-formation regions partitioned by an isolation trench, first and second lower gate insulating films formed on the first and second element-formation regions, first and second floating gates formed on the first and second lower gate insulating films, an isolation insulating film formed at least in the isolation trench and has a depression formed in an upper surface thereof, an upper gate insulating film formed on the first and second floating gates, and a control gate line including an opposed portion opposed to the first and second floating gates, with the upper gate insulating film being interposed, and a portion located inside the depression, the first floating gate including a side surface opposed to the second floating gate and entirely aligns with a side surface included in the first element-formation region and defined by the isolation trench.
    Type: Application
    Filed: March 1, 2007
    Publication date: July 5, 2007
    Inventors: Yoshinori KITAMURA, Shigeki Sugimoto
  • Patent number: 7214580
    Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate including first and second element-formation regions partitioned by an isolation trench, first and second lower gate insulating films formed on the first and second element-formation regions, first and second floating gates formed on the first and second lower gate insulating films, an isolation insulating film formed at least in the isolation trench and has a depression formed in an upper surface thereof, an upper gate insulating film formed on the first and second floating gates, and a control gate line including an opposed portion opposed to the first and second floating gates, with the upper gate insulating film being interposed, and a portion located inside the depression, the first floating gate including a side surface opposed to the second floating gate and entirely aligns with a side surface included in the first element-formation region and defined by the isolation trench.
    Type: Grant
    Filed: December 1, 2004
    Date of Patent: May 8, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshinori Kitamura, Shigeki Sugimoto
  • Patent number: 7207179
    Abstract: A connecting method and structure is provided to reliably ensure the compressive strength of the joint between a heat transfer pipe and a capillary tube when connecting the capillary tube to the heat transfer pipe by direct brazing. In the connection structure between the heat transfer pipe and the capillary tube, a pinched part in which a pipe end part of the capillary tube is inserted and a brazing filler material pooling part for pooling on a pipe end face side of the pinched part the brazing filler material that flows into the pinched part are formed. When inserted into the pinched part, the capillary tube is brazed to the heat transfer pipe.
    Type: Grant
    Filed: May 31, 2004
    Date of Patent: April 24, 2007
    Assignee: Daikin Industries, Ltd.
    Inventors: Yoshinori Kitamura, Nobuhiro Sahara
  • Publication number: 20060275999
    Abstract: A semiconductor device includes a semiconductor substrate formed with a plurality of first element isolation trenches having respective first opening widths and a plurality of second element isolation trenches having larger opening widths than the first opening widths, element isolation insulating films buried in the first element isolation trenches so that upper parts of the trenches have partial openings, respectively and buried in the second element isolation trenches respectively, and coating type oxide films formed so as to fill the openings of the first element isolation trenches, respectively.
    Type: Application
    Filed: June 2, 2006
    Publication date: December 7, 2006
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshinori Kitamura, Koichi Matsuno, Kazunori Nishikawa
  • Publication number: 20060150669
    Abstract: A connecting method and structure is provided to reliably ensure the compressive strength of the joint between a heat transfer pipe and a capillary tube when connecting the capillary tube to the heat transfer pipe by direct brazing. In the connection structure between the heat transfer pipe and the capillary tube, a pinched part in which a pipe end part of the capillary tube is inserted and a brazing filler material pooling part for pooling on a pipe end face side of the pinched part the brazing filler material that flows into the pinched part are formed. When inserted into the pinched part, the capillary tube is brazed to the heat transfer pipe.
    Type: Application
    Filed: May 31, 2004
    Publication date: July 13, 2006
    Applicant: Daikin Industries, Ltd.
    Inventors: Yoshinori Kitamura, Nobuhiro Sahara
  • Patent number: 6969884
    Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate including first and second element-formation regions partitioned by an isolation trench, first and second lower gate insulating films formed on the first and second element-formation regions, first and second floating gates formed on the first and second lower gate insulating films, an isolation insulating film formed at least in the isolation trench and has a depression formed in an upper surface thereof, an upper gate insulating film formed on the first and second floating gates, and a control gate line including an opposed portion opposed to the first and second floating gates, with the upper gate insulating film being interposed, and a portion located inside the depression, the first floating gate including a side surface opposed to the second floating gate and entirely aligns with a side surface included in the first element-formation region and defined by the isolation trench.
    Type: Grant
    Filed: December 8, 2003
    Date of Patent: November 29, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshinori Kitamura, Shigeki Sugimoto
  • Publication number: 20050093080
    Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate including first and second element-formation regions partitioned by an isolation trench, first and second lower gate insulating films formed on the first and second element-formation regions, first and second floating gates formed on the first and second lower gate insulating films, an isolation insulating film formed at least in the isolation trench and has a depression formed in an upper surface thereof, an upper gate insulating film formed on the first and second floating gates, and a control gate line including an opposed portion opposed to the first and second floating gates, with the upper gate insulating film being interposed, and a portion located inside the depression, the first floating gate including a side surface opposed to the second floating gate and entirely aligns with a side surface included in the first element-formation region and defined by the isolation trench.
    Type: Application
    Filed: December 1, 2004
    Publication date: May 5, 2005
    Inventors: Yoshinori Kitamura, Shigeki Sugimoto
  • Publication number: 20050051834
    Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate including first and second element-formation regions partitioned by an isolation trench, first and second lower gate insulating films formed on the first and second element-formation regions, first and second floating gates formed on the first and second lower gate insulating films, an isolation insulating film formed at least in the isolation trench and has a depression formed in an upper surface thereof, an upper gate insulating film formed on the first and second floating gates, and a control gate line including an opposed portion opposed to the first and second floating gates, with the upper gate insulating film being interposed, and a portion located inside the depression, the first floating gate including a side surface opposed to the second floating gate and entirely aligns with a side surface included in the first element-formation region and defined by the isolation trench.
    Type: Application
    Filed: December 8, 2003
    Publication date: March 10, 2005
    Inventors: Yoshinori Kitamura, Shigeki Sugimoto
  • Publication number: 20040027229
    Abstract: In a semiconductive ceramic which has a positive resistance temperature characteristic and is used as a degaussing thermistor element, the current attenuation characteristic is slowly changed without increasing the size of the element by setting a resistance temperature coefficient &agr; in the range of from about 10 to 17.
    Type: Application
    Filed: May 30, 2003
    Publication date: February 12, 2004
    Inventors: Yasuhiro Nabika, Mitsugu Takada, Hiroki Tanaka, Yoshinori Kitamura
  • Patent number: 6617955
    Abstract: An inexpensive positive temperature coefficient thermistor has metal terminals which have been miniaturized without deteriorating the characteristics or sacrificing the reliability of the device. The metal terminals include supporting members and springs constructed such that a total width of the supporting members is smaller than a total width of the springs. In addition, connecting portions at the upper ends of the metal terminals engage with a case main body or a covering member to be retained at predetermined positions.
    Type: Grant
    Filed: January 22, 2002
    Date of Patent: September 9, 2003
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Hiroki Tanaka, Yoshinori Kitamura
  • Patent number: 6544369
    Abstract: Thin film-like material that has printability, that can have unique surface patterns of various kinds, and that can have a design having an effect that has been never produced, and process of producing it are provided. The thin film-like material has a laminated structure in which an adhesive layer and a metal thin layer are laid in this order on the entire surface or parts of the surface of one or each of opposite sides of a base material A surface of the metal thin layer is formed by transfer process as a smooth surface having a mirror pattern, a surface having a mat pattern, a surface having a hairline pattern, a surface having an embossed pattern, a surface having a hologram pattern or a surface having two or more of those patterns combined appropriately.
    Type: Grant
    Filed: October 26, 2000
    Date of Patent: April 8, 2003
    Assignees: Japan Tobacco Inc., JT Prosprint Co., Ltd.
    Inventors: Yoshinori Kitamura, Shigenobu Matsumoto
  • Patent number: 6508596
    Abstract: A plurality of digital signals having total data rates of n bit/s or less are input to a digital recording device recording digital signals having a data rate of n bit/s. The digital signals are subjected to format-conversion for the digital recording device to be recorded therein. Furthermore, signals having a data rate of n/i1 bit/s or less are subjected to format-conversion to be recorded i1 times in the digital recording device. In the case where the data rate of the digital signals to be input is n/j bit/s, the digital signals are subjected to format-conversion so that the amount of data capable of being recorded per unit time is decreased by i/j; thus, the digital signals are recorded for a long period of time under the condition that the data recording time is prolonged j times.
    Type: Grant
    Filed: August 16, 2000
    Date of Patent: January 21, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Chiyoko Matsumi, Ichiro Arimura, Akira Iketani, Masazumi Yamada, Tatsuro Juri, Yukio Kurano, Yoshinori Kitamura, Chojuro Yamamitsu
  • Publication number: 20020118092
    Abstract: An inexpensive positive temperature coefficient thermistor has metal terminals which have been miniaturized without deteriorating the characteristics or sacrificing the reliability of the device. The metal terminals include supporting members and springs constructed such that a total width of the supporting members is smaller than a total width of the springs. In addition, connecting portions at the upper ends of the metal terminals engage with a case main body or a covering member to be retained at predetermined positions.
    Type: Application
    Filed: January 22, 2002
    Publication date: August 29, 2002
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Hiroki Tanaka, Yoshinori Kitamura
  • Patent number: 6147823
    Abstract: A plurality of digital signals having total data rates of n bit/s or less are input to a digital recording device recording digital signals having a data rate of n bit/s. The digital signals are subjected to format-conversion for the digital recording device to be recorded therein. Furthermore, signals having a data rate of n/i.sub.1 bit/s or less are subjected to format-conversion to be recorded i.sub.1 times in the digital recording device. In the case where the data rate of the digital signals to be input is n/j bit/s, the digital signals are subjected to format-conversion so that the amount of data capable of being recorded per unit time is decreased by i/j; thus, the digital signals are recorded for a long period of time under the condition that the data recording time is prolonged j times.
    Type: Grant
    Filed: July 10, 1997
    Date of Patent: November 14, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Chiyoko Matsumi, Ichiro Arimura, Akira Iketani, Masazumi Yamada, Tatsuro Juri, Yukio Kurano, Yoshinori Kitamura, Chojuro Yamamitsu