Patents by Inventor Yoshinori Kumura

Yoshinori Kumura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230108500
    Abstract: According to one embodiment, a method of manufacturing a memory device including a silicon oxide and a variable resistance element electrically coupled to the silicon oxide, includes: introducing a dopant into the silicon oxide from a first surface of the silicon oxide by ion implantation; and etching the first surface of the silicon oxide with an ion beam.
    Type: Application
    Filed: December 12, 2022
    Publication date: April 6, 2023
    Applicant: Kioxia Corporation
    Inventor: Yoshinori KUMURA
  • Patent number: 11557725
    Abstract: According to one embodiment, a method of manufacturing a memory device including a silicon oxide and a variable resistance element electrically coupled to the silicon oxide, includes: introducing a dopant into the silicon oxide from a first surface of the silicon oxide by ion implantation; and etching the first surface of the silicon oxide with an ion beam.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: January 17, 2023
    Assignee: KIOXIA CORPORATION
    Inventor: Yoshinori Kumura
  • Patent number: 11495636
    Abstract: According to one embodiment, a nonvolatile memory device includes a plurality of wiring line pairs each including a pair of first and second wiring lines extending in a first direction, a plurality of third wiring lines each extending in a second direction intersecting the first direction, and a plurality of memory cells provided between the wiring line pairs and the third wiring lines. Each of the memory cells includes a resistance change memory element connected to the third wiring line, and a switching element structure including a first switching element portion provided between the resistance change memory element and the first wiring line, and a second switching element portion provided between the resistance change memory element and the second wiring line.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: November 8, 2022
    Assignee: KIOXIA CORPORATION
    Inventor: Yoshinori Kumura
  • Publication number: 20220302206
    Abstract: According to one embodiment, a magnetic memory device includes a first interconnect, a second interconnect provided on the upper layer side of the first interconnect, a third interconnect provided on the upper layer side of the second interconnect, a first memory cell provided between the first interconnect and the second interconnect and including a first stacked structure including a magnetic layer, a second memory cell provided between the second interconnect and the third interconnect and including a second stacked structure including a magnetic layer, and a light reflection layer provided on the upper layer side of the first interconnect and on the lower layer side of the third interconnect and having optical reflectance higher than optical transmittance.
    Type: Application
    Filed: June 6, 2022
    Publication date: September 22, 2022
    Applicant: Kioxia Corporation
    Inventor: Yoshinori KUMURA
  • Publication number: 20210288253
    Abstract: According to one embodiment, a method of manufacturing a memory device including a silicon oxide and a variable resistance element electrically coupled to the silicon oxide, includes: introducing a dopant into the silicon oxide from a first surface of the silicon oxide by ion implantation; and etching the first surface of the silicon oxide with an ion beam.
    Type: Application
    Filed: September 9, 2020
    Publication date: September 16, 2021
    Applicant: Kioxia Corporation
    Inventor: Yoshinori KUMURA
  • Patent number: 11069850
    Abstract: According to one embodiment, a magnetic memory device includes a stacked structure including a first magnetic layer having a fixed magnetization direction, a nonmagnetic layer provided on the first magnetic layer, and a second magnetic layer provided on the nonmagnetic layer and having a variable magnetization direction, a first insulating layer provided along a side surface of the stacked structure and having an upper end located at a position lower than an upper end of the side surface of the stacked structure, and a second insulating layer covering the first insulating layer and having an upper end located at a position higher than the upper end of the first insulating layer.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: July 20, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yoshinori Kumura
  • Publication number: 20210083000
    Abstract: According to one embodiment, a nonvolatile memory device includes a plurality of wiring line pairs each including a pair of first and second wiring lines extending in a first direction, a plurality of third wiring lines each extending in a second direction intersecting the first direction, and a plurality of memory cells provided between the wiring line pairs and the third wiring lines. Each of the memory cells includes a resistance change memory element connected to the third wiring line, and a switching element structure including a first switching element portion provided between the resistance change memory element and the first wiring line, and a second switching element portion provided between the resistance change memory element and the second wiring line.
    Type: Application
    Filed: March 12, 2020
    Publication date: March 18, 2021
    Applicant: KIOXIA CORPORATION
    Inventor: Yoshinori KUMURA
  • Publication number: 20210083004
    Abstract: According to one embodiment, a nonvolatile memory device includes a first wiring line extending along a first direction, a second wiring line extending along a second direction intersecting the first direction, and a memory cell connected between the first wiring line and the second wiring line and including a resistance change memory element and a switching element connected in series to the resistance change memory element. The switching element includes a first electrode containing at least one of iridium (Ir) and ruthenium (Ru), a second electrode containing at least one of iridium (Ir) and ruthenium (Ru), and an intermediate layer provided between the first electrode and the second electrode and containing silicon (Si) and oxygen (O).
    Type: Application
    Filed: March 12, 2020
    Publication date: March 18, 2021
    Applicant: KIOXIA CORPORATION
    Inventor: Yoshinori KUMURA
  • Publication number: 20200303627
    Abstract: According to one embodiment, a magnetic memory device includes a stacked structure including a first magnetic layer having a fixed magnetization direction, a nonmagnetic layer provided on the first magnetic layer, and a second magnetic layer provided on the nonmagnetic layer and having a variable magnetization direction, a first insulating layer provided along a side surface of the stacked structure and having an upper end located at a position lower than an upper end of the side surface of the stacked structure, and a second insulating layer covering the first insulating layer and having an upper end located at a position higher than the upper end of the first insulating layer.
    Type: Application
    Filed: September 11, 2019
    Publication date: September 24, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Yoshinori KUMURA
  • Publication number: 20200091228
    Abstract: According to one embodiment, a magnetic memory device includes a first interconnect, a second interconnect provided on the upper layer side of the first interconnect, a third interconnect provided on the upper layer side of the second interconnect, a first memory cell provided between the first interconnect and the second interconnect and including a first stacked structure including a magnetic layer, a second memory cell provided between the second interconnect and the third interconnect and including a second stacked structure including a magnetic layer, and a light reflection layer provided on the upper layer side of the first interconnect and on the lower layer side of the third interconnect and having optical reflectance higher than optical transmittance.
    Type: Application
    Filed: March 14, 2019
    Publication date: March 19, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Yoshinori KUMURA
  • Patent number: 9887237
    Abstract: According to an embodiment, a magnetic storage device includes a semiconductor region including a trench; a gate electrode disposed in the trench; an insulation film covering the gate electrode and provided in a manner to fill the trench; and a magnetoresistive effect element including at least a first ferromagnetic layer, a second ferromagnetic layer, and a non-magnetic layer provided between the first ferromagnetic layer and the second ferromagnetic layer, the non-magnetic layer in a side surface of the magnetoresistive effect element including the non-magnetic layer being provided on a top surface of the insulation film.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: February 6, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shintaro Sakai, Keisuke Nakatsuka, Hiroyuki Kanaya, Yoshinori Kumura, Katsuyuki Fujita
  • Patent number: 9818797
    Abstract: According to one embodiment, a magnetic memory device includes a semiconductor substrate, an insulating region provided on the semiconductor substrate, an electrode plug provided in the insulating region, an amorphous conductive portion provided on the electrode plug and including a part provided in the insulating region, and a stacked structure provided on the amorphous conductive portion and including a magnetic layer.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: November 14, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yoshinori Kumura
  • Publication number: 20170256585
    Abstract: According to one embodiment, a semiconductor memory device includes a substrate having resistance-change elements, a first insulating film provided on the substrate, a nonconductive barrier film provided on the first insulating film, a second insulating film provided on the barrier film, and a first interconnect and a second interconnect provided at a predetermined pitch on the substrate, the first and second interconnects being put through the first insulating film, the nonconductive barrier film and the second insulating film. Each of the first and second interconnects comprises at least two wiring layers.
    Type: Application
    Filed: September 13, 2016
    Publication date: September 7, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Yoshinori KUMURA
  • Patent number: 9691457
    Abstract: According to one embodiment, a magnetic memory device includes a magnetoresistive effect element, and a first layer provided on the magnetoresistive effect element, wherein the first layer includes an upper conductive layer, and a predetermined metal containing conductive layer provided between the magnetoresistive effect element and the upper conductive layer and containing a predetermined metal selected from Pt, Ir, Pd and Au.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: June 27, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Yoshinori Kumura
  • Publication number: 20170141157
    Abstract: According to an embodiment, a magnetic storage device includes a semiconductor region including a trench; a gate electrode disposed in the trench; an insulation film covering the gate electrode and provided in a manner to fill the trench; and a magnetoresistive effect element including at least a first ferromagnetic layer, a second ferromagnetic layer, and a non-magnetic layer provided between the first ferromagnetic layer and the second ferromagnetic layer, the non-magnetic layer in a side surface of the magnetoresistive effect element including the non-magnetic layer being provided on a top surface of the insulation film.
    Type: Application
    Filed: March 9, 2016
    Publication date: May 18, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shintaro SAKAI, Keisuke NAKATSUKA, Hiroyuki KANAYA, Yoshinori KUMURA, Katsuyuki FUJITA
  • Publication number: 20170062521
    Abstract: According to one embodiment, a magnetic memory device includes a semiconductor substrate, an insulating region provided on the semiconductor substrate, an electrode plug provided in the insulating region, an amorphous conductive portion provided on the electrode plug and including a part provided in the insulating region, and a stacked structure provided on the amorphous conductive portion and including a magnetic layer.
    Type: Application
    Filed: March 11, 2016
    Publication date: March 2, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Yoshinori KUMURA
  • Publication number: 20160379696
    Abstract: According to one embodiment, a magnetic memory device includes a magnetoresistive effect element, and a first layer provided on the magnetoresistive effect element, wherein the first layer includes an upper conductive layer, and a predetermined metal containing conductive layer provided between the magnetoresistive effect element and the upper conductive layer and containing a predetermined metal selected from Pt, Ir, Pd and Au.
    Type: Application
    Filed: December 28, 2015
    Publication date: December 29, 2016
    Inventor: Yoshinori KUMURA
  • Publication number: 20160204340
    Abstract: According to one embodiment, a method of manufacturing a magnetic memory device, includes forming a lower structure, the lower structure includes a bottom electrode, an interlayer insulating film surrounding the bottom electrode, and a predetermined element containing portion which is in contact with the bottom electrode and which contains a predetermined element other than an element contained in at least a surface area of the bottom electrode and an element contained in at least a surface area of the interlayer insulating film, forming a stack film including a magnetic layer, on the lower structure, forming a hard mask on the stack film, and etching the stack film to expose the predetermined element containing portion.
    Type: Application
    Filed: July 24, 2015
    Publication date: July 14, 2016
    Inventor: Yoshinori KUMURA
  • Patent number: 9312476
    Abstract: According to one embodiment, a magnetic memory is disclosed. The magnetic memory includes a substrate, and a contact plug provided on the substrate. The contact plug includes a first contact plug, and a second contact plug provided on the first contact plug and having a smaller diameter than that of the first contact plug. The magnetic memory further includes a magnetoresistive element provided on the second contact plug. The diameter of the second contact plug is smaller than that of the magnetoresistive element.
    Type: Grant
    Filed: February 25, 2015
    Date of Patent: April 12, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Yoshinori Kumura
  • Publication number: 20160043135
    Abstract: According to one embodiment, a semiconductor memory device including a memory cell array and peripheral region includes a magnetoresistive element provided in the memory cell array, first contact under the magnetoresistive element and second contact in the peripheral region. A material of the first contact differs from that of the second contact.
    Type: Application
    Filed: February 23, 2015
    Publication date: February 11, 2016
    Inventor: Yoshinori KUMURA