Patents by Inventor Yoshinori Kumura
Yoshinori Kumura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230108500Abstract: According to one embodiment, a method of manufacturing a memory device including a silicon oxide and a variable resistance element electrically coupled to the silicon oxide, includes: introducing a dopant into the silicon oxide from a first surface of the silicon oxide by ion implantation; and etching the first surface of the silicon oxide with an ion beam.Type: ApplicationFiled: December 12, 2022Publication date: April 6, 2023Applicant: Kioxia CorporationInventor: Yoshinori KUMURA
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Patent number: 11557725Abstract: According to one embodiment, a method of manufacturing a memory device including a silicon oxide and a variable resistance element electrically coupled to the silicon oxide, includes: introducing a dopant into the silicon oxide from a first surface of the silicon oxide by ion implantation; and etching the first surface of the silicon oxide with an ion beam.Type: GrantFiled: September 9, 2020Date of Patent: January 17, 2023Assignee: KIOXIA CORPORATIONInventor: Yoshinori Kumura
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Patent number: 11495636Abstract: According to one embodiment, a nonvolatile memory device includes a plurality of wiring line pairs each including a pair of first and second wiring lines extending in a first direction, a plurality of third wiring lines each extending in a second direction intersecting the first direction, and a plurality of memory cells provided between the wiring line pairs and the third wiring lines. Each of the memory cells includes a resistance change memory element connected to the third wiring line, and a switching element structure including a first switching element portion provided between the resistance change memory element and the first wiring line, and a second switching element portion provided between the resistance change memory element and the second wiring line.Type: GrantFiled: March 12, 2020Date of Patent: November 8, 2022Assignee: KIOXIA CORPORATIONInventor: Yoshinori Kumura
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Publication number: 20220302206Abstract: According to one embodiment, a magnetic memory device includes a first interconnect, a second interconnect provided on the upper layer side of the first interconnect, a third interconnect provided on the upper layer side of the second interconnect, a first memory cell provided between the first interconnect and the second interconnect and including a first stacked structure including a magnetic layer, a second memory cell provided between the second interconnect and the third interconnect and including a second stacked structure including a magnetic layer, and a light reflection layer provided on the upper layer side of the first interconnect and on the lower layer side of the third interconnect and having optical reflectance higher than optical transmittance.Type: ApplicationFiled: June 6, 2022Publication date: September 22, 2022Applicant: Kioxia CorporationInventor: Yoshinori KUMURA
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Publication number: 20210288253Abstract: According to one embodiment, a method of manufacturing a memory device including a silicon oxide and a variable resistance element electrically coupled to the silicon oxide, includes: introducing a dopant into the silicon oxide from a first surface of the silicon oxide by ion implantation; and etching the first surface of the silicon oxide with an ion beam.Type: ApplicationFiled: September 9, 2020Publication date: September 16, 2021Applicant: Kioxia CorporationInventor: Yoshinori KUMURA
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Patent number: 11069850Abstract: According to one embodiment, a magnetic memory device includes a stacked structure including a first magnetic layer having a fixed magnetization direction, a nonmagnetic layer provided on the first magnetic layer, and a second magnetic layer provided on the nonmagnetic layer and having a variable magnetization direction, a first insulating layer provided along a side surface of the stacked structure and having an upper end located at a position lower than an upper end of the side surface of the stacked structure, and a second insulating layer covering the first insulating layer and having an upper end located at a position higher than the upper end of the first insulating layer.Type: GrantFiled: September 11, 2019Date of Patent: July 20, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventor: Yoshinori Kumura
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Publication number: 20210083000Abstract: According to one embodiment, a nonvolatile memory device includes a plurality of wiring line pairs each including a pair of first and second wiring lines extending in a first direction, a plurality of third wiring lines each extending in a second direction intersecting the first direction, and a plurality of memory cells provided between the wiring line pairs and the third wiring lines. Each of the memory cells includes a resistance change memory element connected to the third wiring line, and a switching element structure including a first switching element portion provided between the resistance change memory element and the first wiring line, and a second switching element portion provided between the resistance change memory element and the second wiring line.Type: ApplicationFiled: March 12, 2020Publication date: March 18, 2021Applicant: KIOXIA CORPORATIONInventor: Yoshinori KUMURA
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Publication number: 20210083004Abstract: According to one embodiment, a nonvolatile memory device includes a first wiring line extending along a first direction, a second wiring line extending along a second direction intersecting the first direction, and a memory cell connected between the first wiring line and the second wiring line and including a resistance change memory element and a switching element connected in series to the resistance change memory element. The switching element includes a first electrode containing at least one of iridium (Ir) and ruthenium (Ru), a second electrode containing at least one of iridium (Ir) and ruthenium (Ru), and an intermediate layer provided between the first electrode and the second electrode and containing silicon (Si) and oxygen (O).Type: ApplicationFiled: March 12, 2020Publication date: March 18, 2021Applicant: KIOXIA CORPORATIONInventor: Yoshinori KUMURA
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Publication number: 20200303627Abstract: According to one embodiment, a magnetic memory device includes a stacked structure including a first magnetic layer having a fixed magnetization direction, a nonmagnetic layer provided on the first magnetic layer, and a second magnetic layer provided on the nonmagnetic layer and having a variable magnetization direction, a first insulating layer provided along a side surface of the stacked structure and having an upper end located at a position lower than an upper end of the side surface of the stacked structure, and a second insulating layer covering the first insulating layer and having an upper end located at a position higher than the upper end of the first insulating layer.Type: ApplicationFiled: September 11, 2019Publication date: September 24, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventor: Yoshinori KUMURA
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Publication number: 20200091228Abstract: According to one embodiment, a magnetic memory device includes a first interconnect, a second interconnect provided on the upper layer side of the first interconnect, a third interconnect provided on the upper layer side of the second interconnect, a first memory cell provided between the first interconnect and the second interconnect and including a first stacked structure including a magnetic layer, a second memory cell provided between the second interconnect and the third interconnect and including a second stacked structure including a magnetic layer, and a light reflection layer provided on the upper layer side of the first interconnect and on the lower layer side of the third interconnect and having optical reflectance higher than optical transmittance.Type: ApplicationFiled: March 14, 2019Publication date: March 19, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventor: Yoshinori KUMURA
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Patent number: 9887237Abstract: According to an embodiment, a magnetic storage device includes a semiconductor region including a trench; a gate electrode disposed in the trench; an insulation film covering the gate electrode and provided in a manner to fill the trench; and a magnetoresistive effect element including at least a first ferromagnetic layer, a second ferromagnetic layer, and a non-magnetic layer provided between the first ferromagnetic layer and the second ferromagnetic layer, the non-magnetic layer in a side surface of the magnetoresistive effect element including the non-magnetic layer being provided on a top surface of the insulation film.Type: GrantFiled: March 9, 2016Date of Patent: February 6, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Shintaro Sakai, Keisuke Nakatsuka, Hiroyuki Kanaya, Yoshinori Kumura, Katsuyuki Fujita
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Patent number: 9818797Abstract: According to one embodiment, a magnetic memory device includes a semiconductor substrate, an insulating region provided on the semiconductor substrate, an electrode plug provided in the insulating region, an amorphous conductive portion provided on the electrode plug and including a part provided in the insulating region, and a stacked structure provided on the amorphous conductive portion and including a magnetic layer.Type: GrantFiled: March 11, 2016Date of Patent: November 14, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventor: Yoshinori Kumura
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Publication number: 20170256585Abstract: According to one embodiment, a semiconductor memory device includes a substrate having resistance-change elements, a first insulating film provided on the substrate, a nonconductive barrier film provided on the first insulating film, a second insulating film provided on the barrier film, and a first interconnect and a second interconnect provided at a predetermined pitch on the substrate, the first and second interconnects being put through the first insulating film, the nonconductive barrier film and the second insulating film. Each of the first and second interconnects comprises at least two wiring layers.Type: ApplicationFiled: September 13, 2016Publication date: September 7, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Yoshinori KUMURA
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Patent number: 9691457Abstract: According to one embodiment, a magnetic memory device includes a magnetoresistive effect element, and a first layer provided on the magnetoresistive effect element, wherein the first layer includes an upper conductive layer, and a predetermined metal containing conductive layer provided between the magnetoresistive effect element and the upper conductive layer and containing a predetermined metal selected from Pt, Ir, Pd and Au.Type: GrantFiled: December 28, 2015Date of Patent: June 27, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventor: Yoshinori Kumura
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Publication number: 20170141157Abstract: According to an embodiment, a magnetic storage device includes a semiconductor region including a trench; a gate electrode disposed in the trench; an insulation film covering the gate electrode and provided in a manner to fill the trench; and a magnetoresistive effect element including at least a first ferromagnetic layer, a second ferromagnetic layer, and a non-magnetic layer provided between the first ferromagnetic layer and the second ferromagnetic layer, the non-magnetic layer in a side surface of the magnetoresistive effect element including the non-magnetic layer being provided on a top surface of the insulation film.Type: ApplicationFiled: March 9, 2016Publication date: May 18, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Shintaro SAKAI, Keisuke NAKATSUKA, Hiroyuki KANAYA, Yoshinori KUMURA, Katsuyuki FUJITA
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Publication number: 20170062521Abstract: According to one embodiment, a magnetic memory device includes a semiconductor substrate, an insulating region provided on the semiconductor substrate, an electrode plug provided in the insulating region, an amorphous conductive portion provided on the electrode plug and including a part provided in the insulating region, and a stacked structure provided on the amorphous conductive portion and including a magnetic layer.Type: ApplicationFiled: March 11, 2016Publication date: March 2, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Yoshinori KUMURA
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Publication number: 20160379696Abstract: According to one embodiment, a magnetic memory device includes a magnetoresistive effect element, and a first layer provided on the magnetoresistive effect element, wherein the first layer includes an upper conductive layer, and a predetermined metal containing conductive layer provided between the magnetoresistive effect element and the upper conductive layer and containing a predetermined metal selected from Pt, Ir, Pd and Au.Type: ApplicationFiled: December 28, 2015Publication date: December 29, 2016Inventor: Yoshinori KUMURA
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Publication number: 20160204340Abstract: According to one embodiment, a method of manufacturing a magnetic memory device, includes forming a lower structure, the lower structure includes a bottom electrode, an interlayer insulating film surrounding the bottom electrode, and a predetermined element containing portion which is in contact with the bottom electrode and which contains a predetermined element other than an element contained in at least a surface area of the bottom electrode and an element contained in at least a surface area of the interlayer insulating film, forming a stack film including a magnetic layer, on the lower structure, forming a hard mask on the stack film, and etching the stack film to expose the predetermined element containing portion.Type: ApplicationFiled: July 24, 2015Publication date: July 14, 2016Inventor: Yoshinori KUMURA
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Patent number: 9312476Abstract: According to one embodiment, a magnetic memory is disclosed. The magnetic memory includes a substrate, and a contact plug provided on the substrate. The contact plug includes a first contact plug, and a second contact plug provided on the first contact plug and having a smaller diameter than that of the first contact plug. The magnetic memory further includes a magnetoresistive element provided on the second contact plug. The diameter of the second contact plug is smaller than that of the magnetoresistive element.Type: GrantFiled: February 25, 2015Date of Patent: April 12, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventor: Yoshinori Kumura
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Publication number: 20160043135Abstract: According to one embodiment, a semiconductor memory device including a memory cell array and peripheral region includes a magnetoresistive element provided in the memory cell array, first contact under the magnetoresistive element and second contact in the peripheral region. A material of the first contact differs from that of the second contact.Type: ApplicationFiled: February 23, 2015Publication date: February 11, 2016Inventor: Yoshinori KUMURA