Abstract: Provided is a reception device which can reduce a parallel interference canceller processing delay.

Abstract: A transmitting apparatus, receiving apparatus and communication system are disclosed, and great improvement in an S/N ratio, preventing an actual throughput from decreasing, and preventing the number of circuits for synchronizing spread spectrum signals from increasing can be expected at the receiving apparatus side. The transmitting apparatus includes a pulse generating circuit, pulse repetition cycle determining circuit, peak power determining circuit, and modulator. The pulse generating circuit generates pulse strings, pulse repetition cycle determining circuit determines, based on a clock signal, a pulse repetition cycle of the pulse string generated by the pulse generating circuit. The peak power determining circuit determines a pulse peak power of the pulse string. The modulator modulates the pulse string with transmission data, and then generates a transmission signal.

Abstract: An impulse radio communication device includes a wave detector for generating a detected signal, a switching section for selecting either a received signal or the detected signal in accordance with an external control signal and outputting it as a demodulation target signal, a reference waveform generating section synchronized with the demodulation target signal and generating a reference waveform signal having a different waveform in accordance with the external control signal, a demodulator for generating a demodulated signal from the demodulation target signal in accordance with the reference waveform signal, and a decoding section for decoding received data from the demodulated signal. This impulse radio communication device switches the demodulation target signal and the reference waveform signal simultaneously in accordance with a receiving and synchronizing state.

Abstract: A relay apparatus, terminal apparatus and relay method for relaying signals with a reduced scale of the apparatus, without temporally switching between transmission and reception and with reduced waste of time when relay is performed at the same frequency on a radio communication network on which bidirectional communication is performed. A radio reception section 202 outputs information signals to a switch 208, outputs relay control signals to a demodulation section 204 after subjecting predetermined radio reception processing. The demodulation section 204 demodulates a relay control signal. A relay control signal processing section 206 decides the possibility of relay of information signals and inquires, when the relay is possible, whether the terminal apparatus on the receiving side can receive this information signal or not. Furthermore, the relay control signal processing section 206 connects a switch 208 during the stored relay time.

Abstract: A pulse modulation type transmitter apparatus and a pulse modulation type receiver apparatus wherein both a fast synchronization establishment and a low power consumption of a synchronizing part can be achieved at the same time and wherein the data transmission/reception can be performed soon after a commencement of communication, and further a fast data transmission and a low power consumption can be achieved. A first template signal (1006), which is generated based on a separately transmitted RF frame synchronization signal (1005), is used to generate a frame synchronization signal (1009), and a second frame synchronization timing adjusting part (150) is used to synchronize the frame synchronization signal (1009) with a received RF data signal (1004). Then, a synchronization detection is performed, whereby a prompt pulse acquisition and a prompt pulse phase acquisition can be achieved.

Abstract: A master side communication apparatus and a slave side communication apparatus wherein the structure of a receiving part of the slave side communication apparatus is simplified to achieve a reduced size, a reduced power consumption and a reduced cost. The master side communication apparatus performs a communication in synchronism with the slave side communication apparatus having no synchronization timing adjusting function. A transport signal generating timing adjusting part of the master side communication apparatus acquires, from the slave side communication apparatus, synchronization signal generation timing information used when the slave side communication apparatus receives the transport signal from the master side communication apparatus. The transport signal generating timing adjusting part varies and adjusts, based on the acquired information, the transmission timing of the signal to be transmitted to the slave side communication apparatus.

Abstract: An impulse radio communication device includes a wave detector for generating a detected signal, a switching section for selecting either a received signal or the detected signal in accordance with an external control signal and outputting it as a demodulation target signal, a reference waveform generating section synchronized with the demodulation target signal and generating a reference waveform signal having a different waveform in accordance with the external control signal, a demodulator for generating a demodulated signal from the demodulation target signal in accordance with the reference waveform signal, and a decoding section for decoding received data from the demodulated signal. This impulse radio communication device switches the demodulation target signal and the reference waveform signal simultaneously in accordance with a receiving and synchronizing state.

Abstract: A loop interference canceller that carries out an adaptive operation of responding to time variations of the phase or level of loop interference wave or key station wave at high speed and with high accuracy and reduces the size of an apparatus. The loop interference canceller of the present invention limits the number of data pieces of the transmission path characteristic estimation section, realizes expansion to the entire band not through interpolation but through 0 insertion in a frequency domain and windowing after time domain transformation to reduce the number of data pieces processed and speed up the adaptive operation of the loop interference canceller, and can thereby realize high trackability for time variations of the phase and level of loop interference wave or key station wave, increase the accuracy of processing inside, perform high accuracy cancellation operation, reduce the circuit scale and achieve an advantageous effect of realizing miniaturization of the apparatus.

Abstract: A communication system includes a modulating circuit to increase the amount of information to be transmitted, a transmitting apparatus capable of easily generating a desired waveform even for any very short wavelets, a receiving apparatus capable of easily separating wavelets even if the intervals thereof are narrow. The modulating circuit includes clock generating, transmission signal generating, control signal generating, delay and wavelet generating parts. The clock generating part generates a clock signal at predetermined time interval “Tp”. The transmission signal generating part generates a transmission signal at interval “Tp”. The control signal generating part outputs a control signal of a predetermined duration based on the clock signal. The delay part generates the control signal as a delay signal that has been delayed by a delay amount based on the transmission signal. The wavelet generating part generates a wavelet at the generation timing of the delay signal.

Abstract: An A/D conversion section performs oversampling on an analog signal at a rate M times a symbol rate to convert the analog signal into a digital signal. A FIR filtering section has two delay-element sequences, each with a plurality of delay elements. The two delay-element sequences have different delay directions, i.e., a forward direction and a reverse direction. The delay directions can be switched, and according to a finite impulse response train having such delay-element sequences, a convolutional calculation is performed. A phase determining section determines a phase used in making a decision in a decision section. The decision section makes a decision on a filtered signal using the phase determined in the phase determining section to generate bit data. A digital signal receiving apparatus is thus achieved which determines a phase with a high accuracy without increasing the oversampling number, and performs a fast calculation while having a reduced circuitry scale.

Abstract: An A/D conversion section performs oversampling on an analog signal at a rate M times a symbol rate to convert the analog signal into a digital signal. A FIR filtering section has two delay-element sequences, each with a plurality of delay elements. The two delay-element sequences have different delay directions, i.e., a forward direction and a reverse direction. The delay directions can be switched, and according to a finite impulse response train having such delay-element sequences, a convolutional calculation is performed. A phase determining section determines a phase used in making a decision in a decision section. The decision section makes a decision on a filtered signal using the phase determined in the phase determining section to generate bit data. A digital signal receiving apparatus is thus achieved which determines a phase with a high accuracy without increasing the oversampling number, and performs a fast calculation while having a reduced circuitry scale.

Abstract: A loop interference canceller that carries out an adaptive operation of responding to time variations of the phase or level of loop interference wave or key station wave at high speed and with high accuracy and reduces the size of an apparatus. The loop interference canceller of the present invention limits the number of data pieces of the transmission path characteristic estimation section, realizes expansion to the entire band not through interpolation but through 0 insertion in a frequency domain and windowing after time domain transformation to reduce the number of data pieces processed and speed up the adaptive operation of the loop interference canceller, and can thereby realize high trackability for time variations of the phase and level of loop interference wave or key station wave, increase the accuracy of processing inside, perform high accuracy cancellation operation, reduce the circuit scale and achieve an advantageous effect of realizing miniaturization of the apparatus.

Abstract: A relay apparatus, terminal apparatus and relay method for relaying signals with a reduced scale of the apparatus, without temporally switching between transmission and reception and with reduced waste of time when relay is performed at the same frequency on a radio communication network on which bidirectional communication is performed. A radio reception section 202 outputs information signals to a switch 208, outputs relay control signals to a demodulation section 204 after subjecting predetermined radio reception processing. The demodulation section 204 demodulates a relay control signal. A relay control signal processing section 206 decides the possibility of relay of information signals and inquires, when the relay is possible, whether the terminal apparatus on the receiving side can receive this information signal or not. Furthermore, the relay control signal processing section 206 connects a switch 208 during the stored relay time.

Abstract: An A/D conversion section (101) performs oversampling on an analog signal at a rate M times the symbol rate to convert into digital signals. A FIR filtering section (102) has two delay-element sequences each with a plurality of delay elements, and the two sequences have different delay directions of input signal, i.e., forward direction and reverse direction. The delay directions of input signal can be switched, and according to the finite impulse response train having such delay-element sequences, convolutional calculation is performed. A phase determining section (103) determines a phase used in making a decision in a decision section (104). The decision section (104) makes a decision on a filtered signal using the phase determined in the phase determining section (103) to generate bit data. A digital signal receiving apparatus is thus achieved which determines a phase with high accuracy without increasing the oversampling number, and performs fast calculation while having a reduced circuitry scale.

Abstract: Wiring is variably connected between delay section 102 having N delay elements, D0 to DN-1, and multiplying section 104 having N multipliers, c(0) to c(N-1). Further, wiring is variably connected between multiplying section 104 and adding section 106 having N adders, K0 to KN-1. When the oversampling number of an input signal is dynamically varied, wiring control section 109 varies the wiring so as to obtain a filter structure with a number of parallels corresponding to the oversampling number. Thus, the finite impulse response filter is capable of responding to the dynamically varied oversampling number, and reducing its circuit size.

Abstract: A demodulation apparatus of the present invention comprises: an A/D converter for sampling and quantizing a baseband signal; a transversal filter having time-shifted tap coefficients; a decision unit for decoding the signal which has undergone the transversal filter; and a decision point estimation unit for instructing the transversal filter to select the tap coefficient to be selected based on information from the decision unit. Thus, the demodulation apparatus can operate at the same frequency as a sampling frequency of the A/D converter and can perform decision with accuracy equivalent to an arbitrary oversampling number.

Abstract: A demodulation apparatus of the present invention comprises: an A/D converter for sampling and quantizing a baseband signal; a transversal filter having time-shifted tap coefficients; a decision unit for decoding the signal which has undergone the transversal filter; and a decision point estimation unit for instructing the transversal filter to select the tap coefficient to be selected based on information from the decision unit. Thus, the demodulation apparatus can operate at the same frequency as a sampling frequency of the A/D converter and can perform decision with accuracy equivalent to an arbitrary oversampling number.

Abstract: A receiving ckt for receiving a transmitted SIG including FRQ divided carriers, comprises: a FRQ conversion ckt responsive to the LO SIG with a LO for generating a LO SIG with LO FRQ controlled according to a FRQ CONT SIG for FRQ converting the transmitted SIG into an IF SIG; a orthogonal signal separation ckt separating the IF SIG into I and Q components; a complex FFT conversion ckt for complex FFT converting the I and Q components and outputting conversion SIGs to be decoded arranged in FRQ base; an ELEC PWR measurement ckt measuring values of ELEC PWRs of the conversion SIGs; and a prediction ckt for predicting a CTR FRQ of the FRQ divided carriers from a FRQ distribution of the values of ELEC PWRs from the ELEC PWR measurement ckt and generating the FRQ CONT SIG according to the predicted center FRQ. The CTR FRQ may be detected by a REF carrier detection ckt responsive to the complex FFT processing ckt detecting a REF carrier or a carrier pattern included in the transmitted SIG.

Abstract: A timing signal generator includes a demodulator for an input modulated signal to provide first and second baseband signals having a quadrature relation relative to each other. A converter is used to convert the first and second baseband signals into angle data representing a phase, and a calculator is used to calculate a difference between the phase represented by current angle data and the phase represented by previous angle data, preceding the current angle data by a 1-symbol interval. The calculator outputs data representative of the calculated phase difference. A further converter converts the calculator output data into a binary reference signal responsive to which of predetermined divided regions contains a point corresponding to the calculated difference data. Also included is a generator for generating a symbol timing signal in synchronism with the binary reference signal.

Abstract: In a frame synchronizing apparatus for a receiver apparatus of a digital data radio communications system in which data are transmitted in frame periods with a fixed data sequence contained each frame, a data correlation circuit obtains successive sequences of values of vector difference between vector values constituting a demodulated digital baseband signal, and successively compares these sequences with a fixed vector difference sequence corresponding to the fixed data sequence, to derive a correlation signal substantially unaffected by any phase rotation in the baseband signal. A frame synchronizing circuit formed as a PLL for generating a frame synchronizing signal, includes a phase comparator which periodically indicates whether a detected phase difference between the correlation signal and frame synchronizing signal is effectively zero, positive or negative, and a counter holding a count value indicating a cumulative phase error between these signals.