Patents by Inventor Yoshinori Matsuno
Yoshinori Matsuno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11935919Abstract: A method for manufacturing a semiconductor device includes forming, on first and second impurity layers on a termination region side, an insulating layer, forming a first metal film and a second metal film in this order on the insulating layer and a drift layer, performing dry etching on the first and second metal films all together so that a position of a first end of a metallized layer, which is a remaining part of the first metal film, in the interface region on the termination region side and a position of a second end of an electrode, which is a remaining part of the second metal film, in the interface region on the terminal region side are the same in plan view. The first and second ends are closer to the active region than an end of the second impurity layer on the termination region side in plan view.Type: GrantFiled: August 1, 2022Date of Patent: March 19, 2024Assignee: Mitsubishi Electric CorporationInventors: Yoshinori Matsuno, Yasushi Takaki, Kensuke Taguchi, Kosuke Miyazaki
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Publication number: 20240029571Abstract: A flight support apparatus includes a flight support unit that displays a reference flight profile that is a flight profile as a reference, the flight profile indicating a flight specification at a plurality of spots included in a path from a departure place to a destination, corrects the reference flight profile according to a flight condition input by a user to prepare a corrected flight profile, and displays the prepared corrected flight profile together with the reference flight profile.Type: ApplicationFiled: September 1, 2021Publication date: January 25, 2024Inventors: Tomoko IIJIMA, Yoshinori MATSUNO, Noboru MOTOYAMA, Koji ITO
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Publication number: 20220367613Abstract: A method for manufacturing a semiconductor device includes forming, on first and second impurity layers on a termination region side, an insulating layer, forming a first metal film and a second metal film in this order on the insulating layer and a drift layer, performing dry etching on the first and second metal films all together so that a position of a first end of a metallized layer, which is a remaining part of the first metal film, in the interface region on the termination region side and a position of a second end of an electrode, which is a remaining part of the second metal film, in the interface region on the terminal region side are the same in plan view. The first and second ends are closer to the active region than an end of the second impurity layer on the termination region side in plan view.Type: ApplicationFiled: August 1, 2022Publication date: November 17, 2022Applicant: Mitsubishi Electric CorporationInventors: Yoshinori MATSUNO, Yasushi TAKAKI, Kensuke TAGUCHI, Kosuke MIYAZAKI
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Patent number: 11437465Abstract: A semiconductor device includes an insulating layer provided on a first impurity layer and a second impurity layer on a termination region side, a metallized layer provided on the first impurity layer and the second impurity layer exposed from the insulating layer and on the insulating layer, and an electrode provided on the metallized layer. A position of a first end of the metallized layer on the termination region side and a position of a second end of the electrode on the termination region side are the same in plan view.Type: GrantFiled: April 10, 2020Date of Patent: September 6, 2022Assignee: Mitsubishi Electric CorporationInventors: Yoshinori Matsuno, Yasushi Takaki, Kensuke Taguchi, Kosuke Miyazaki
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Publication number: 20220051575Abstract: [Object] To suppress the influence of uncertainties on a time of arrival while reducing the number of speed adjustments or the like to suppress the deterioration of fuel efficiency and comfort.Type: ApplicationFiled: August 29, 2019Publication date: February 17, 2022Inventor: Yoshinori MATSUNO
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Patent number: 11088073Abstract: In some examples, a semiconductor device includes a substrate, an interlayer insulating film, a gate pad provided on the interlayer insulating film, a source electrode that is provided on the interlayer insulating film, source wiring provided on the interlayer insulating film, and gate wiring that is provided on the interlayer insulating film and is electrically connected to the gate pad. The size of the source wiring is not increased, and a high impurity concentration region having a higher impurity concentration than a drift layer is formed on the surface of the substrate at a location directly below the gate pad.Type: GrantFiled: February 5, 2020Date of Patent: August 10, 2021Assignee: Mitsubishi Electric CorporationInventors: Yoshinori Matsuno, Toshikazu Tanioka, Yasunori Oritsuki, Kenichi Hamano, Naochika Hanano
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Publication number: 20200395439Abstract: A semiconductor device includes an insulating layer provided on a first impurity layer and a second impurity layer on a termination region side, a metallized layer provided on the first impurity layer and the second impurity layer exposed from the insulating layer and on the insulating layer, and an electrode provided on the metallized layer. A position of a first end of the metallized layer on the termination region side and a position of a second end of the electrode on the termination region side are the same in plan view.Type: ApplicationFiled: April 10, 2020Publication date: December 17, 2020Applicant: Mitsubishi Electric CorporationInventors: Yoshinori MATSUNO, Yasushi TAKAKI, Kensuke TAGUCHI, Kosuke MIYAZAKI
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Publication number: 20200303296Abstract: In some examples, a semiconductor device includes a substrate, an interlayer insulating film, a gate pad provided on the interlayer insulating film, a source electrode that is provided on the interlayer insulating film, source wiring provided on the interlayer insulating film, and gate wiring that is provided on the interlayer insulating film and is electrically connected to the gate pad. The size of the source wiring is not increased, and a high impurity concentration region having a higher impurity concentration than a drift layer is formed on the surface of the substrate at a location directly below the gate pad.Type: ApplicationFiled: February 5, 2020Publication date: September 24, 2020Applicant: Mitsubishi Electric CorporationInventors: Yoshinori MATSUNO, Toshikazu TANIOKA, Yasunori ORITSUKI, Kenichi HAMANO, Naochika HANANO
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Patent number: 9276068Abstract: A silicon oxide film is formed on an epitaxial layer by dry thermal oxidation, an ohmic electrode is formed on a back surface of a SiC substrate, an ohmic junction is formed between the ohmic electrode and the back surface of the SiC substrate by annealing the SiC substrate, the silicon oxide film is removed, and a Schottky electrode is formed on the epitaxial layer. Then, a sintering treatment is performed to form a Schottky junction between the Schottky electrode and the epitaxial layer.Type: GrantFiled: October 3, 2013Date of Patent: March 1, 2016Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Yoshinori Matsuno, Yoichiro Tarui
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Patent number: 9263525Abstract: The present invention includes an n+ type substrate, a drift epitaxial layer formed on the n+ type substrate and having a lower concentration of impurity than the n+ type substrate, a Schottky electrode formed on the drift epitaxial layer, and a PI formed as an insulating film by covering at least an end of the Schottky electrode and an end and a side surface of the drift epitaxial layer.Type: GrantFiled: January 7, 2013Date of Patent: February 16, 2016Assignee: Mitsubishi Electric CorporationInventor: Yoshinori Matsuno
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Patent number: 8685848Abstract: A silicon oxide film is formed on an epitaxial layer by dry thermal oxidation, an ohmic electrode is formed on a back surface of a SiC substrate, an ohmic junction is formed between the ohmic electrode and the back surface of the SiC substrate by annealing the SiC substrate, the silicon oxide film is removed, and a Schottky electrode is formed on the epitaxial layer. Then, a sintering treatment is performed to form a Schottky junction between the Schottky electrode and the epitaxial layer.Type: GrantFiled: January 23, 2012Date of Patent: April 1, 2014Assignee: Mitsubishi Electric CorporationInventors: Yoshinori Matsuno, Yoichiro Tarui
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Patent number: 8680538Abstract: In order to obtain a silicon carbide semiconductor device that ensures both stability of withstand voltage and reliability in high-temperature operations in its termination end-portion provided for electric-field relaxation in the perimeter of a cell portion driven as a semiconductor element, the termination end-portion is provided with an inorganic protection film having high heat resistance that is formed on an exposed surface of a well region as a first region formed on a side of the cell portion, and an organic protection film having a high electrical insulation capability with a little influence by electric charges that is formed on a surface of an electric-field relaxation region formed in contact relation to an outer lateral surface of the well region and apart from the cell portion, and on an exposed surface of the silicon carbide layer.Type: GrantFiled: February 12, 2008Date of Patent: March 25, 2014Assignee: Mitsubishi Electric CorporationInventors: Yoichiro Tarui, Kenichi Ohtsuka, Naruhisa Miura, Yoshinori Matsuno, Masayuki Imaizumi
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Publication number: 20140038397Abstract: A silicon oxide film is formed on an epitaxial layer by dry thermal oxidation, an ohmic electrode is formed on a back surface of a SiC substrate, an ohmic junction is formed between the ohmic electrode and the back surface of the SiC substrate by annealing the SiC substrate, the silicon oxide film is removed, and a Schottky electrode is formed on the epitaxial layer. Then, a sintering treatment is performed to form a Schottky junction between the Schottky electrode and the epitaxial layer.Type: ApplicationFiled: October 3, 2013Publication date: February 6, 2014Applicant: Mitsubishi Electric CorporationInventors: Yoshinori MATSUNO, Yoichiro Tarui
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Patent number: 8569123Abstract: An object is to provide a method for manufacturing a silicon carbide semiconductor device in which a time required for removing a sacrificial oxide film can be shortened and damage to a surface of the silicon carbide layer can be reduced. The method for manufacturing a silicon carbide semiconductor device includes: (a) performing ion implantation to a silicon carbide layer; (b) performing activation annealing to the ion-implanted silicon carbide layer 2; (c) removing a surface layer of the silicon carbide layer 2, to which the activation annealing has been performed, by dry etching; (d) forming a sacrificial oxide film on a surface layer of the silicon carbide layer, to which the dry etching has been performed, by performing sacrificial oxidation thereto; and (e) removing the sacrificial oxide film by wet etching.Type: GrantFiled: September 1, 2009Date of Patent: October 29, 2013Assignee: Mitsubishi Electric CorporationInventors: Yoshinori Matsuno, Kenichi Ohtsuka, Naoki Yutani, Kenichi Kuroda, Hiroshi Watanabe, Shozo Shikama
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Publication number: 20130234160Abstract: The present invention includes an n+ type substrate, a drift epitaxial layer formed on the n+ type substrate and having a lower concentration of impurity than the n+ type substrate, a Schottky electrode formed on the drift epitaxial layer, and a PI formed as an insulating film by covering at least an end of the Schottky electrode and an end and a side surface of the drift epitaxial layer.Type: ApplicationFiled: January 7, 2013Publication date: September 12, 2013Inventor: Yoshinori MATSUNO
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Patent number: 8377811Abstract: An object of the invention is to provide a method for manufacturing a silicon carbide semiconductor device having constant characteristics with reduced variations in forward characteristics. The method for manufacturing the silicon carbide semiconductor device according to the invention includes the steps of: (a) preparing a silicon carbide substrate; (b) forming an epitaxial layer on a first main surface of the silicon carbide substrate; (c) forming a protective film on the epitaxial layer; (d) forming a first metal layer on a second main surface of the silicon carbide substrate; (e) applying heat treatment to the silicon carbide substrate at a predetermined temperature to form an ohmic junction between the first metal layer and the second main surface of the silicon carbide substrate; (f) removing the protective film; (g) forming a second metal layer on the epitaxial layer; and (h) applying heat treatment to the silicon carbide substrate at a temperature from 400° C. to 600° C.Type: GrantFiled: August 8, 2008Date of Patent: February 19, 2013Assignee: Mitsubishi Electric CorporationInventors: Yoshinori Matsuno, Kenichi Ohtsuka, Kenichi Kuroda, Shozo Shikama, Naoki Yutani
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Publication number: 20120302051Abstract: A silicon oxide film is formed on an epitaxial layer by dry thermal oxidation, an ohmic electrode is formed on a back surface of a SiC substrate, an ohmic junction is formed between the ohmic electrode and the back surface of the SiC substrate by annealing the SiC substrate, the silicon oxide film is removed, and a Schottky electrode is formed on the epitaxial layer. Then, a sintering treatment is performed to form a Schottky junction between the Schottky electrode and the epitaxial layer.Type: ApplicationFiled: January 23, 2012Publication date: November 29, 2012Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Yoshinori MATSUNO, Yoichiro Tarui
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Patent number: 8304901Abstract: In a termination structure in which a JTE layer is provided, a level or defect existing at an interface between a semiconductor layer and an insulating film, or a minute amount of adventitious impurities that infiltrate into the semiconductor interface from the insulating film or from an outside through the insulating film becomes a source or a breakdown point of a leakage current, which deteriorates a breakdown voltage.Type: GrantFiled: March 12, 2009Date of Patent: November 6, 2012Assignee: Mitsubishi Electric CorporationInventors: Hiroshi Watanabe, Naoki Yutani, Kenichi Ohtsuka, Kenichi Kuroda, Masayuki Imaizumi, Yoshinori Matsuno
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Publication number: 20120028453Abstract: An object is to provide a method for manufacturing a silicon carbide semiconductor device in which a time required for removing a sacrificial oxide film can be shortened and damage to a surface of the silicon carbide layer can be reduced. The method for manufacturing a silicon carbide semiconductor device includes: (a) performing ion implantation to a silicon carbide layer; (b) performing activation annealing to the ion-implanted silicon carbide layer 2; (c) removing a surface layer of the silicon carbide layer 2, to which the activation annealing has been performed, by dry etching; (d) forming a sacrificial oxide film on a surface layer of the silicon carbide layer, to which the dry etching has been performed, by performing sacrificial oxidation thereto; and (e) removing the sacrificial oxide film by wet etching.Type: ApplicationFiled: September 1, 2009Publication date: February 2, 2012Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Yoshinori Matsuno, Kenichi Ohtsuka, Naoki Yutani, Kenichi Kuroda, Hiroshi Watanabe, Shozo Shikama
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Publication number: 20110001209Abstract: In a termination structure in which a JTE layer is provided, a level or defect existing at an interface between a semiconductor layer and an insulating film, or a minute amount of adventitious impurities that infiltrate into the semiconductor interface from the insulating film or from an outside through the insulating film becomes a source or a breakdown point of a leakage current, which deteriorates a breakdown voltage.Type: ApplicationFiled: March 12, 2009Publication date: January 6, 2011Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Hiroshi Watanabe, Naoki Yutani, Kenichi Ohtsuka, Kenichi Kuroda, Masayuki Imaizumi, Yoshinori Matsuno