Patents by Inventor Yoshinori Nagoya
Yoshinori Nagoya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080271781Abstract: This invention provides a CIS-based thin film solar battery and a process for producing the same in which the formation of an alkali barrier layer and a metal backside electrode layer is carried out at a low cost in a short time to prevent such an unfavorable phenomenon that a light absorbing layer is separated from the interface of the light absorbing layer and the metal backside electrode layer. The CIS-based thin film solar battery (1) comprises a glass substrate (2), an alkali-free layer (7) such as silica, a metal backside electrode layer (3) having a laminate structure, a p-type CIS-based light absorbing layer (4), a high-resistance buffer layer (5), and an n-type window layer (6) stacked in that order. The layer (7), either alone or together with a first layer (3a) in the layer (3), can function as an alkali barrier layer (8) that can prevent and control the thermal diffusion of an alkali component into the light absorbing layer during the formation of the layer (4) from the substrate (2).Type: ApplicationFiled: December 9, 2005Publication date: November 6, 2008Applicant: SHOWA SHELL SEKIYU K. K.Inventors: Katsumi Kushiya, Yoshiaki Tanaka, Masaru Onodera, Manabu Tanaka, Yoshinori Nagoya
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Publication number: 20070289624Abstract: Film formation is conducted at a low temperature to improve conversion efficiency and productivity and to enable a wider choice of substrate materials to be used. The invention relates to the light absorption layer of a CIS compound semiconductor thin-film solar cell and to a method of forming the layer. The light absorption layer comprises a compound represented by Cux(In1-yGay)(Se1-zSz)2 and having a chalcopyrite type structure, the proportions of the components satisfying 0.86?x?0.98, 0.05?y?0.25, 0?z?0.3, x=?T+?, ?=0.015y?0.00025, and ?=?7.9y+1.105, provided that T (° C.) is anneal temperature and the allowable range for x is ±0.02. The layer is formed by the selenization method at a low temperature (about 500?T?550). As the substrate is used a soda-lime glass having a low melting point.Type: ApplicationFiled: August 9, 2005Publication date: December 20, 2007Applicant: SHOWA SHELL SEKIYU K.K.Inventors: Satoru Kuriyagawa, Yoshinori Nagoya, Yoshiaki Tanaka
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Publication number: 20070283998Abstract: A precursor film having a required gallium component proportion is formed easily at low cost. A precursor film for use in forming the light absorption layer of a CIS type thin-film solar cell, etc., or a method for forming the film are provided. A Cu—Ga layer having a high gallium component proportion (Ga/(Ga+Cu)) of X % by weight Ga is formed as a first layer by sputtering using a precursor film comprising a Cu—Ga alloy layer having the gallium component proportion of X % by weight Ga as a target (deposition step A). Thereafter, a copper layer is formed as a second layer on the first layer by sputtering using a copper layer as a target (deposition step B) to thereby form a precursor film having the required gallium component proportion of Y % (X>Y) by weight Ga as the sum of the first layer and second layer. A method of film formation by simultaneous vapor deposition is also possible.Type: ApplicationFiled: December 27, 2005Publication date: December 13, 2007Applicant: SHOWA SHELL SEKIYU K.K.Inventors: Satoru Kuriyagawa, Yoshiaki Tanaka, Yoshinori Nagoya
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Patent number: 6856709Abstract: The provision of a coplanar waveguide coupled with a microstrip line with a transmission line substrate that is used between two functional units of different impedance characteristics allows the input and output impedance matching to be performed, the impedance matching between which coplanar waveguide and microstrip line is performed by the variation of the signal linewidth. It allows the transmission characteristics of the optical transmission device in high frequency band to improve.Type: GrantFiled: March 28, 2002Date of Patent: February 15, 2005Assignee: OpNext Japan, Inc.Inventors: Kouichi Uesaka, Takashi Suga, Hisaaki Kanai, Yoshinori Nagoya
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Publication number: 20030091258Abstract: The provision of a coplanar waveguide coupled with a microstrip line with a transmission line substrate that is used between two functional units of different impedance characteristics allows the input and output impedance matching to be performed, the impedance matching between which coplanar waveguide and microstrip line is performed by the variation of the signal linewidth. It allows the transmission characteristics of the optical transmission device in high frequency band to improve.Type: ApplicationFiled: March 28, 2002Publication date: May 15, 2003Applicant: OpNext Japan, Inc.Inventors: Kouichi Uesaka, Takashi Suga, Hisaaki Kanai, Yoshinori Nagoya
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Patent number: 6091305Abstract: It is an object of the present invention to reduce the amount of spurious noise generated by an emission line spectrum of a signal propagating around the PLL of a PLL frequency synthesizer carrying out digital-signal processing.In order to achieve the object described above, the present invention provides a PLL frequency synthesizer with the following configuration.In a PLL frequency synthesizer having a charge-pump circuit, a waveform converter is provided at a stage behind the charge-pump circuit. The waveform converter converts the voltage waveform on a time axis of a rectangular wave output by the charge-pump circuit into a waveform which: is symmetrical with respect to a predetermined point of time; oscillates so as to have no direct-current component; and has a maximum value of the absolute values of maximums of wave heights thereof located at the center wherein the absolute value decreases uniformly as the wave height is separated farther away from the center.Type: GrantFiled: August 6, 1999Date of Patent: July 18, 2000Assignee: Hitachi, Ltd.Inventors: Yoshinori Nagoya, Yuji Ishida, Ken Takei
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Patent number: 5977838Abstract: The present invention designs and implements a high-speed PLL circuit and a high-speed synthesizer using the high-speed PLL circuit which has an increased switching speed, a reduced number of jitters and a reduced magnitude of spurious response. In order to achieve the above, the present invention provides a PLL circuit forming a closed loop wherein: one of the inputs of a phase comparator 1 serves as the input of the PLL circuit and the output of phase comparator 1 is connected to the input of a loop filter 2; the output of loop filter 2 is connected to the input of a voltage-controlled oscillator (VCO) 3; the output of the VCO 3 serves as the output of the PLL circuit; and the output of the VCO 3 is supplied to the other input of phase comparator 1 through a frequency divider 4. The circuit form and circuit constants of loop filter 2 are determined so that the transfer function of the closed loop becomes a Gaussian function.Type: GrantFiled: April 24, 1997Date of Patent: November 2, 1999Assignee: Hitachi Ltd.Inventors: Yoshinori Nagoya, Yuji Ishida, Ken Takei
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Patent number: 5963099Abstract: It is an object of the present invention to reduce the amount of spurious noise generated by an emission line spectrum of a signal propagating around the PLL of a PLL frequency synthesizer carrying out digital-signal processing.In order to achieve the object described above, the present invention provides a PLL frequency synthesizer with the following configuration.In a PLL frequency synthesizer having a charge-pump circuit, a waveform converter is provided at a stage behind the charge-pump circuit. The waveform converter converts the voltage waveform on a time axis of a rectangular wave output by the charge-pump circuit into a waveform which: is symmetrical with respect to a predetermined point of time; oscillates so as to have no direct-current component; and has a maximum value of the absolute values of maximums of wave heights thereof located at the center wherein the absolute value decreases uniformly as the wave height is separated farther away from the center.Type: GrantFiled: March 4, 1997Date of Patent: October 5, 1999Assignee: Hitachi, Ltd.Inventors: Yoshinori Nagoya, Yuji Ishida, Ken Takei
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Output-controlled power amplifier, radio communication terminal and radio communication base station
Patent number: 5854971Abstract: In an output-controlled power amplifier of a closed loop type, an input signal is inputted to a main path in which the input signal is power-attenuated by a variable attenuator and power-amplified by a power amplifier. A power divider distributes the amplified input signal between the main path and a feedback path diverging from the main path so that the signal distributed to the main path is outputted from the main path to the exterior while the input signal is controlled on the basis of the signal distributed to the feedback path. The feedback path includes a hold circuit for extracting the signal distributed to the feedback path and holding the value of the power of the extracted signal when the power reaches a predetermined value. A control signal for attenuating the power of the input signal inputted to the main path is generated by the hold circuit and is applied through the feedback path to the variable attenuator on the main path to control the power of the input signal.Type: GrantFiled: March 27, 1996Date of Patent: December 29, 1998Assignee: Hitachi, Ltd.Inventors: Yoshinori Nagoya, Takashi Sakai, Yuji Ishida, Ken Takei -
Patent number: 4187479Abstract: A variable equalizer is provided which, using a single variable resistor, can make compensations in both the directions of the gain side, and the loss side and can set a reference gain as desired.An input signal to be equalized is received as an antiphase input signal of a differential amplifier, an output signal which has been equalized is fed back to the antiphase input signal, and a difference signal between an in-phase input signal and the antiphase input signal is delivered as an output. A resistor is connected between an input terminal and ground, first and second impedance circuits and a variable resistor are connected between an intermediate point of the first-mentioned resistor and ground in the order mentioned, and a voltage at the junction point between the first and second impedance circuits is used as the in-phase input signal.Type: GrantFiled: December 13, 1977Date of Patent: February 5, 1980Assignee: Hitachi, Ltd.Inventors: Kohei Ishizuka, Yoshitaka Takasaki, Yasuhiro Kita, Yoshinori Nagoya, Takeo Kusama
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Patent number: 4122417Abstract: To form a simple and economical variable equalizer, the equalizer is constructed of a differential amplifier having two input terminals to which an input signal to be equalized and an equalized output signal derived from the output terminal are applied, a first impedance circuit connected between the differential amplifier and the output terminal, and a series circuit having a second impedance circuit and a variable resistor connected in series between the output terminal and a ground terminal.Type: GrantFiled: May 13, 1977Date of Patent: October 24, 1978Assignee: Hitachi, Ltd.Inventors: Yoshitaka Takasaki, Kohei Ishizuka, Yasuhiro Kita, Yoshinori Nagoya, Takeo Kusama
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Patent number: 4080580Abstract: In order to realize a precision variable equalizer of little errors by a simple circuit arrangement, a plurality of variable transmission circuits having variable transfer coefficients are connected in series between input and output terminals, and feed-back and feed-forward are applied from input and output sides of the respective variable transmission circuits to input and output portions of the variable equalizer through transmission networks having specified transfer characteristics.Type: GrantFiled: November 4, 1976Date of Patent: March 21, 1978Assignee: Hitachi, Ltd.Inventors: Yoshitaka Takasaki, Yasuhiro Kita, Jun'ichi Nakagawa, Kohei Ishizuka, Osamu Yumoto, Yoshinori Nagoya