Patents by Inventor Yoshinori Nakanishi

Yoshinori Nakanishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10773280
    Abstract: An ultrasonic treatment apparatus including: an ultrasonic bath for performing an ultrasonic treatment on a treatment target object; a first ultrasonic vibrator provided on the front surface side of the treatment target object; and a second ultrasonic vibrator provided on the back surface side of the treatment target object; wherein the first ultrasonic vibrator does not face the second ultrasonic vibrator.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: September 15, 2020
    Assignee: C. UYEMURA & CO., LTD.
    Inventors: Hisamitsu Yamamoto, Masayuki Utsumi, Yoshikazu Saijo, Tomoji Okuda, Yutaka Nishinaka, Yoshinori Nakanishi
  • Publication number: 20190140546
    Abstract: A switching power supply comprising: a feedback element; a voltage detection element which is connected to the feedback element at secondary side of the switching power supply and changes current which flows to the feedback element based on output voltage of the switching power supply; a control circuit which is connected to the feedback element at primary side of the switching power supply and controls the switching element; and a current detection resistor which is connected to the switching element, wherein the controller circuit controls burst mode or normal mode based on voltage which is occurred in a first terminal which is connected between the current detection resistor and the switching element and a value based on voltage which is occurred in a second terminal which is connected to the feedback element, sets the switching element ON until the voltage which is occurred in the first terminal reaches to the value based on the voltage which is occurred in the second terminal, and sets the switching elem
    Type: Application
    Filed: May 4, 2018
    Publication date: May 9, 2019
    Inventors: Kei ASAO, Yoshinori NAKANISHI
  • Publication number: 20190132677
    Abstract: A signal processing device configured to perform: low pass filter processing to extract a low frequency component of an audio signal, compression processing to compress the audio signal to which the low pass filter processing is performed in a case that the audio signal to which the low pass filter processing is performed is not less than a predetermined signal level, high pass filter processing to extract high frequency component of the audio signal, first volume processing to attenuate the audio signal, and synthesis processing to synthesize the low frequency component of the audio signal to which the compression processing is performed and high frequency component of the audio signal.
    Type: Application
    Filed: October 26, 2018
    Publication date: May 2, 2019
    Inventors: Hiroki KUROSAKI, Tsuyoshi KAWAGUCHI, Yoshinori NAKANISHI, Norimasa KITAGAWA
  • Patent number: 10149053
    Abstract: To resolve volume shortage of middle and high band of speaker reproduction sound. A DSP 4 performs LPF processing to extract low frequency component of an audio signal to which the first volume processing is performed, DRC processing to compress the audio signal to which the LPF processing is performed in case that the audio signal to which the LPF processing is performed is not less than a predetermined signal level, HPF processing to extract high frequency component of the audio signal to which the first volume processing is performed, second volume processing to attenuate the audio signal to which the HPF processing is performed based on the volume value that is received, and synthesis processing to synthesize the audio signal to which the DRC processing is performed and the audio signal to which the second volume processing is performed.
    Type: Grant
    Filed: July 22, 2017
    Date of Patent: December 4, 2018
    Assignee: Onkyo Corporation
    Inventors: Hiroki Kurosaki, Tsuyoshi Kawaguchi, Yoshinori Nakanishi, Hiroyuki Asahara, Norimasa Kitagawa
  • Publication number: 20180133760
    Abstract: An ultrasonic treatment apparatus including: an ultrasonic bath for performing an ultrasonic treatment on a treatment target object; a first ultrasonic vibrator provided on the front surface side of the treatment target object; and a second ultrasonic vibrator provided on the back surface side of the treatment target object; wherein the first ultrasonic vibrator does not face the second ultrasonic vibrator.
    Type: Application
    Filed: November 1, 2017
    Publication date: May 17, 2018
    Inventors: Hisamitsu YAMAMOTO, Masayuki UTSUMI, Yoshikazu SAIJO, Tomoji OKUDA, Yutaka NISHINAKA, Yoshinori NAKANISHI
  • Publication number: 20180041836
    Abstract: To resolve volume shortage of middle and high band of speaker reproduction sound. A DSP 4 performs LPF processing to extract low frequency component of an audio signal to which the first volume processing is performed, DRC processing to compress the audio signal to which the LPF processing is performed in case that the audio signal to which the LPF processing is performed is not less than a predetermined signal level, HPF processing to extract high frequency component of the audio signal to which the first volume processing is performed, second volume processing to attenuate the audio signal to which the HPF processing is performed based on the volume value that is received, and synthesis processing to synthesize the audio signal to which the DRC processing is performed and the audio signal to which the second volume processing is performed.
    Type: Application
    Filed: July 22, 2017
    Publication date: February 8, 2018
    Inventors: Hiroki KUROSAKI, Tsuyoshi KAWAGUCHI, Yoshinori NAKANISHI, Hiroyuki ASAHARA, Norimasa KITAGAWA
  • Patent number: 9787319
    Abstract: Provided is a modulation circuit that can correct an output state in real time and reliably modulate an input signal to output the modulated signal. The signal modulation circuit includes a subtractor, an integrator, a chopper circuit, a frequency divider, and a D-type flip-flop. A delay circuit of a sigma delta modulation circuit is not provided to a feedback circuit, and a signal is delayed and quantized in the D-type flip-flop. The chopper circuit inserts a zero level at timing synchronized with a clock signal, so that pulse density modulation is performed.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: October 10, 2017
    Assignee: Onkyo Corporation
    Inventors: Yoshinori Nakanishi, Tsuyoshi Kawaguchi, Mamoru Sekiya
  • Patent number: 9762197
    Abstract: To realize active control ground that sets inverted output of an amplification circuit to ground with simple configuration. A DAP 1 comprises a positive side DAC 7 that D/A-converts digital audio data into analog audio data, a positive side amplification circuit 9 that amplifies the analog audio data that the DAC 7 D/A-converts, a negative side DAC 8 that D/A-converts the digital audio data into the analog audio data, and a negative side amplification circuit 10 that amplifies the analog audio data that the DAC 8 D/A-converts, and a CPU 2. The CPU 2 mutes the DAC 8 in case of an ACG mode that sets output of the amplification circuit 10 to ground.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: September 12, 2017
    Assignee: ONKYO Corporation
    Inventors: Kei Asao, Tsuyoshi Kawaguchi, Makoto Yoshida, Takanori Shiozaki, Yoshinori Nakanishi, Hiroyuki Asahara, Norimasa Kitagawa
  • Patent number: 9712919
    Abstract: To reduce signal output and wiring to a D/A converter (DAC). A DAP 1 comprises a DAC 7 that D/A-converts LR 2 channels digital audio data into LR 2 channels analog audio data, an amplification circuit 9 that amplifies the LR 2 channels analog audio data that the DAC 7 D/A-converts, a DAC 8 that D/A-converts the LR 2 channels digital audio data into the LR 2 channels analog audio data, and an amplification circuit 10 that amplifies inverted LR 2 channels analog audio data that the LR 2 channels analog audio data that the DAC 8 D/A-converts is inverted.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: July 18, 2017
    Assignee: Onkyo Corporation
    Inventors: Kei Asao, Tsuyoshi Kawaguchi, Makoto Yoshida, Takanori Shiozaki, Yoshinori Nakanishi, Hiroyuki Asahara, Norimasa Kitagawa
  • Patent number: 9590654
    Abstract: Provided is a circuit which can correct an output state in real time and reduce influences of distortion/noise components generated by a delay device. A signal modulation circuit includes a subtractor, an integrator, a phase inverting circuit, a DFF for while inserting a zero level at timing synchronous with the clock signal, delaying and quantizing the signal, a ternary signal generating circuit for generating a ternary signal for selectively driving a load connected to a single power supply into ternary conductive states including a positive current on-state, a negative current on-state, and an off-state, a driver circuit for generating a driving signal for driving a load, and a feedback circuit for feeding back the driving signal from the driver circuit to the input signal.
    Type: Grant
    Filed: January 12, 2015
    Date of Patent: March 7, 2017
    Assignee: Onkyo Corporation
    Inventors: Yoshinori Nakanishi, Tsuyoshi Kawaguchi, Mamoru Sekiya
  • Publication number: 20170064455
    Abstract: To reduce signal output and wiring to a D/A converter (DAC). A DAP 1 comprises a DAC 7 that D/A-converts LR 2 channels digital audio data into LR 2 channels analog audio data, an amplification circuit 9 that amplifies the LR 2 channels analog audio data that the DAC 7 D/A-converts, a DAC 8 that D/A-converts the LR 2 channels digital audio data into the LR 2 channels analog audio data, and an amplification circuit 10 that amplifies inverted LR 2 channels analog audio data that the LR 2 channels analog audio data that the DAC 8 D/A-converts is inverted.
    Type: Application
    Filed: August 16, 2016
    Publication date: March 2, 2017
    Inventors: Kei ASAO, Tsuyoshi KAWAGUCHI, Makoto YOSHIDA, Takanori SHIOZAKI, Yoshinori NAKANISHI, Hiroyuki ASAHARA, Norimasa KITAGAWA
  • Publication number: 20170063320
    Abstract: To realize active control ground that sets inverted output of an amplification circuit to ground with simple configuration. A DAP 1 comprises a positive side DAC 7 that D/A-converts digital audio data into analog audio data, a positive side amplification circuit 9 that amplifies the analog audio data that the DAC 7 D/A-converts, a negative side DAC 8 that D/A-converts the digital audio data into the analog audio data, and a negative side amplification circuit 10 that amplifies the analog audio data that the DAC 8 D/A-converts, and a CPU 2. The CPU 2 mutes the DAC 8 in case of an ACG mode that sets output of the amplification circuit 10 to ground.
    Type: Application
    Filed: August 16, 2016
    Publication date: March 2, 2017
    Inventors: Kei ASAO, Tsuyoshi KAWAGUCHI, Makoto YOSHIDA, Takanori SHIOZAKI, Yoshinori NAKANISHI, Hiroyuki ASAHARA, Norimasa KITAGAWA
  • Patent number: 9444488
    Abstract: A signal modulation circuit includes a feedback circuit configured to generate the feedback signal for feeding back a drive signal from a driver circuit to an input signal. The feedback circuit includes at least first and second resistors connected together in series, the second resistor having a higher resistance value than that of the first resistor. One end of the first resistor is connected to a subtracter, and one end of the second resistor is connected to the driver circuit. A first line distance as the line length between one end of the first resistor and the subtracter and a second line distance as the line length between one end of the second resistor and the driver circuit are set shorter than a third line distance as the line length between the other end of the first resistor and the other end of the second resistor.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: September 13, 2016
    Assignee: Onkyo Corporation
    Inventors: Tsuyoshi Kawaguchi, Yoshinori Nakanishi
  • Publication number: 20160241256
    Abstract: Provided is a modulation circuit that can correct an output state in real time and reliably modulate an input signal to output the modulated signal. The signal modulation circuit includes a subtractor, an integrator, a chopper circuit, a frequency divider, and a D-type flip-flop. A delay circuit of a sigma delta modulation circuit is not provided to a feedback circuit, and a signal is delayed and quantized in the D-type flip-flop. The chopper circuit inserts a zero level at timing synchronized with a clock signal, so that pulse density modulation is performed.
    Type: Application
    Filed: April 25, 2016
    Publication date: August 18, 2016
    Inventors: Yoshinori NAKANISHI, Tsuyoshi KAWAGUCHI, Mamoru SEKIYA
  • Patent number: 9350378
    Abstract: Provided is a modulation circuit that can correct an output state in real time and reliably modulate an input signal to output the modulated signal. The signal modulation circuit includes a subtracter, an integrator, a chopper circuit, a frequency divider, and a D-type flip-flop. A delay circuit of a sigma delta modulation circuit is not provided to a feedback circuit, and a signal is delayed and quantized in the D-type flip-flop. The chopper circuit inserts a zero level at timing synchronized with a clock signal, so that pulse density modulation is performed.
    Type: Grant
    Filed: June 4, 2014
    Date of Patent: May 24, 2016
    Assignee: Onkyo Corporation
    Inventors: Yoshinori Nakanishi, Tsuyoshi Kawaguchi, Mamoru Sekiya
  • Patent number: 9287867
    Abstract: A circuit having versatility synthesizes one-bit digital signals to generate a ternary signal. The pulse synthesizing circuit synthesizes one-bit digital signals from two DFFs to generate a ternary signal. The pulse synthesizing circuit has a first NOR gate, a second NOR gate, a third NOR gate, and three switches. The first switch is connected to a first electric potential, the second switch is connected to a second electric potential, and the third switch is connected to a third electric potential. The first to third switches are turned on/off according to logical values of the signals from the two DFFs, and any of the first electric potential, the second electric potential, and the third electric potential is set as an output potential so that a ternary signal is generated.
    Type: Grant
    Filed: June 4, 2014
    Date of Patent: March 15, 2016
    Assignee: Onkyo Corporation
    Inventors: Yoshinori Nakanishi, Tsuyoshi Kawaguchi, Mamoru Sekiya
  • Patent number: 9240783
    Abstract: A circuit having versatility synthesizes one-bit digital signals to generate a ternary signal. The pulse synthesizing circuit synthesizes one-bit digital signals from two DFFs to generate a ternary signal. The pulse synthesizing circuit has a first NOR gate, a second NOR gate, a third NOR gate, and three switches. The first switch is connected to a first electric potential, the second switch is connected to a second electric potential, and the third switch is connected to a third electric potential. The first to third switches are turned on/off according to logical values of the signals from the two DFFs, and any of the first electric potential, the second electric potential, and the third electric potential is set as an output potential so that a ternary signal is generated.
    Type: Grant
    Filed: June 4, 2014
    Date of Patent: January 19, 2016
    Assignee: Onkyo Corporation
    Inventors: Yoshinori Nakanishi, Tsuyoshi Kawaguchi, Mamoru Sekiya
  • Publication number: 20150207519
    Abstract: Provided is a circuit which can correct an output state in real time and reduce influences of distortion/noise components generated by a delay device. A signal modulation circuit includes a subtractor, an integrator, a phase inverting circuit, a DFF for while inserting a zero level at timing synchronous with the clock signal, delaying and quantizing the signal, a ternary signal generating circuit for generating a ternary signal for selectively driving a load connected to a single power supply into ternary conductive states including a positive current on-state, a negative current on-state, and an off-state, a driver circuit for generating a driving signal for driving a load, and a feedback circuit for feeding back the driving signal from the driver circuit to the input signal.
    Type: Application
    Filed: January 12, 2015
    Publication date: July 23, 2015
    Inventors: Yoshinori NAKANISHI, Tsuyoshi KAWAGUCHI, Mamoru SEKIYA
  • Patent number: 8970269
    Abstract: A pulse width modulation signal with a less distortion component that is not influenced by a common-mode noise or an offset voltage is generated. Pulse signal generation circuits 6, 7 generate pulse signals S1, S2 whose pulse widths are discharge times t1, t2 of integrators 3, 4, respectively, a PWM signal generation circuit 8 detects discharge end timings of the integrators 3, 4 based on the pulse signals S1, S2, and a pulse whose pulse width is a time between discharge end timing of one of the integrators 4 and discharge end timing of the other one of the integrators 3 is generated so as to be output as a PWM signal Spwm.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: March 3, 2015
    Assignee: Onkyo Corporation
    Inventors: Yoshinori Nakanishi, Mamoru Sekiya
  • Publication number: 20140363032
    Abstract: Provided is a modulation circuit that can correct an output state in real time and reliably modulate an input signal to output the modulated signal. The signal modulation circuit includes a subtracter, an integrator, a chopper circuit, a frequency divider, and a D-type flip-flop. A delay circuit of a sigma delta modulation circuit is not provided to a feedback circuit, and a signal is delayed and quantized in the D-type flip-flop. The chopper circuit inserts a zero level at timing synchronized with a clock signal, so that pulse density modulation is performed.
    Type: Application
    Filed: June 4, 2014
    Publication date: December 11, 2014
    Inventors: Yoshinori NAKANISHI, Tsuyoshi KAWAGUCHI, Mamoru SEKIYA