Abstract: The disclosure provides a signaling link that overcomes or at least reduces the limitations of RC-dominated signaling wires, improving both the bandwidth and the power consumption of signaling circuits. Both an AC and a DC signaling link are disclosed. In one example, a signaling link is provided that includes: (1) a transmitter including a passive equalizer, (2) an over-terminated receiver, and (3) a lossy channel having a first end connected to the passive equalizer and a second end connected to the receiver, wherein the lossy channel has a channel characteristic impedance that is lower than a terminating impedance of the passive equalizer and a termination impedance of the receiver.

Abstract: A simultaneous bi-directional (SBD) transceiver includes a main transmit driver, a replica transmit driver, and a series-series-bridged (SSB) tri-impedance network. A pre-driver stage includes parallel delay paths for the main transmit driver and the replica transmit driver, enabling the delay for signals received by the main transmit driver and the replica transmit driver to be independently configured.

Abstract: An exemplary differential output buffer includes a mixing stage and an output stage. The mixing stage includes a mixing circuit that mixes a differential data signal and an inverted delayed differential data signal to generate a mixed differential data signal. The output stage includes a first and a second output stage differential pair of transistors. Sources of the transistors in each of the output stage differential pairs are commonly coupled. Gates of the transistors in the first and second output stage differential pairs are supplied with the differential data signal and the mixed differential data signal, respectively. Drains of corresponding ones of the transistors in the first and second output stage differential pairs are commonly connected to form output nodes to output an emphasized differential data signal. The mixing stage includes a mixing ratio setting circuit that sets the mixing ratio to one of 1:0, 1:1, and 0:1.

Abstract: Apparatus and method for receiving burst data signal without using external detection signal are disclosed. The apparatus can include a clock data recovery (CDR) circuit to generate a clock signal, and a detection circuit to detect an initial portion in the data recovered from the input signal. The CDR circuit can have a first mode that attempts to synchronize the clock signal with a reference data signal, and a second mode that attempts to synchronize the clock signal with the burst data signal and to recover data based on the clock signal. The apparatus can include a controller to conduct a process including, in sequence, setting the CDR circuit in the first mode, setting the CDR circuit in the second mode, and keeping the CDR circuit in the second mode when the detection circuit detects the initial portion in the recovered data.

Abstract: An approach is provided for a low-voltage, high-accuracy current mirror circuit. In one example, a current mirror circuit includes an input circuit configured to receive an input reference current. The input circuit includes a feedback channel for comparing and substantially matching the input reference current with an output current. The feedback channel is not configured for matching an input voltage with an output voltage. The input circuit does not include a comparator having an operational amplifier to compare the input reference current with the output current. The current mirror circuit also includes an output circuit coupled to the input circuit. The output circuit is configured to send the output current to one or more components of a circuit block.

Abstract: Apparatus and method for receiving burst data signal without using external detection signal are disclosed. The apparatus can include a clock data recovery (CDR) circuit to generate a clock signal, and a detection circuit to detect an initial portion in the data recovered from the input signal. The CDR circuit can have a first mode that attempts to synchronize the clock signal with a reference data signal, and a second mode that attempts to synchronize the clock signal with the burst data signal and to recover data based on the clock signal. The apparatus can include a controller to conduct a process including, in sequence, setting the CDR circuit in the first mode, setting the CDR circuit in the second mode, and keeping the CDR circuit in the second mode when the detection circuit detects the initial portion in the recovered data.

Abstract: An output driver circuit including a pre-driver stage that receives a first data signal, the pre-driver stage including a plurality of first differential pairs that perform current subtraction to output a second data signal based on the first data signal, and an output driver stage electrically coupled to the pre-driver stage that receives the second data signal from the pre-driver stage, the output driver stage including a plurality of second differential pairs that transmit an output signal along transmission lines.

Abstract: Apparatus and method for receiving burst data signal without using external detection signal are disclosed. The apparatus can include a clock data recovery (CDR) circuit to generate a clock signal, and a detection circuit to detect an initial portion in the data recovered from the input signal. The CDR circuit can have a first mode that attempts to synchronize the clock signal with a reference data signal, and a second mode that attempts to synchronize the clock signal with the burst data signal and to recover data based on the clock signal. The apparatus can include a controller to conduct a process including, in sequence, setting the CDR circuit in the first mode, setting the CDR circuit in the second mode, and keeping the CDR circuit in the second mode when the detection circuit detects the initial portion in the recovered data.

Abstract: An operating device for a manual transmission apparatus includes: a plurality of operation shafts, supported at a housing to move in an axial direction thereof and selectively engaging one of a plurality of shift gear sets by one of the plurality of the operation shafts being moved in the axial direction thereof; a shift-and-select shaft, supported at the housing, selecting one of the plurality of the operation shafts by rotating in a circumferential direction of the shift-and-select shaft and moving the selected operation shaft in the axial direction of the selected operation shaft by moving in the axial direction of the shift-and-select shaft; an operating portion for manually operating the shift-and-select shaft; and an inertia unit, including an engagement portion, which is engageable with the shift-and-select shaft, pivotably supported at the housing, and pivoting in response to a movement of the shift-and-select shaft in the axial direction thereof.

Abstract: An output driver circuit including a pre-driver stage that receives a first data signal, the pre-driver stage including a plurality of first differential pairs that perform current subtraction to output a second data signal based on the first data signal, and an output driver stage electrically coupled to the pre-driver stage that receives the second data signal from the pre-driver stage, the output driver stage including a plurality of second differential pairs that transmit an output signal along transmission lines.

Abstract: An exemplary differential output buffer includes a mixing stage and an output stage. The mixing stage includes a mixing circuit that mixes a differential data signal and an inverted delayed differential data signal to generate a mixed differential data signal. The output stage includes a first and a second output stage differential pair of transistors. Sources of the transistors in each of the output stage differential pairs are commonly coupled. Gates of the transistors in the first and second output stage differential pairs are supplied with the differential data signal and the mixed differential data signal, respectively. Drains of corresponding ones of the transistors in the first and second output stage differential pairs are commonly connected to form output nodes to output an emphasized differential data signal. The mixing stage includes a mixing ratio setting circuit that sets the mixing ratio to one of 1:0, 1:1, and 0:1.

Abstract: An output driver circuit including a pre-driver stage that receives a first data signal, the pre-driver stage including a plurality of first differential pairs that perform current subtraction to output a second data signal based on the first data signal, and an output driver stage electrically coupled to the pre-driver stage that receives the second data signal from the pre-driver stage, the output driver stage including a plurality of second differential pairs that transmit an output signal along transmission lines.

Abstract: Apparatus and method for receiving burst data signal without using external detection signal are disclosed. The apparatus can include a clock data recovery (CDR) circuit to generate a clock signal, and a detection circuit to detect an initial portion in the data recovered from the input signal. The CDR circuit can have a first mode that attempts to synchronize the clock signal with a reference data signal, and a second mode that attempts to synchronize the clock signal with the burst data signal and to recover data based on the clock signal. The apparatus can include a controller to conduct a process including, in sequence, setting the CDR circuit in the first mode, setting the CDR circuit in the second mode, and keeping the CDR circuit in the second mode when the detection circuit detects the initial portion in the recovered data.

Abstract: Apparatus and method for receiving burst data signal without using external detection signal are disclosed. The apparatus can include a clock data recovery (CDR) circuit to generate a clock signal, and a detection circuit to detect an initial portion in the data recovered from the input signal. The CDR circuit can have a first mode that attempts to synchronize the clock signal with a reference data signal, and a second mode that attempts to synchronize the clock signal with the burst data signal and to recover data based on the clock signal. The apparatus can include a controller to conduct a process including, in sequence, setting the CDR circuit in the first mode, setting the CDR circuit in the second mode, and keeping the CDR circuit in the second mode when the detection circuit detects the initial portion in the recovered data.

Abstract: An operating device for a manual transmission apparatus includes: a plurality of operation shafts, supported at a housing to move in an axial direction thereof and selectively engaging one of a plurality of shift gear sets by one of the plurality of the operation shafts being moved in the axial direction thereof; a shift-and-select shaft, supported at the housing, selecting one of the plurality of the operation shafts by rotating in a circumferential direction of the shift-and-select shaft and moving the selected operation shaft in the axial direction of the selected operation shaft by moving in the axial direction of the shift-and-select shaft; an operating portion for manually operating the shift-and-select shaft; and an inertia unit, including an engagement portion, which is engageable with the shift-and-select shaft, pivotably supported at the housing, and pivoting in response to a movement of the shift-and-select shaft in the axial direction thereof.

Abstract: An electric power steering apparatus comprises a transmission mechanism for transmitting driving force of a steering assisting electric motor to a steering mechanism. A driven gear of the transmission mechanism is rotatably supported by first and second bearings. One of the first and second bearings includes an inner ring coupled so as to be rotatable together with an output shaft of a steering shaft, an outer ring held on a housing, and a rolling element interposed between the inner ring and the outer ring. One of the inner ring and the outer ring includes an annular elastic plate giving a preload to the rolling element.

Abstract: Aspects of the disclosure provide a method for calibrating a circuit performance. The method can stabilize the circuit performance over time, and maintain the circuit performance substantially in a specification independent of various variation sources. Therefore, chip reliability can be improved and high product yield can be achieved. The method for calibrating the circuit performance can include assigning levels to a set of circuit parameters of a circuit, measuring values of the circuit parameters during operation of the circuit, generating a control signal that corresponds to the measured circuit parameters weighted according to the assigned levels, and adjusting a feedback relationship of a feedback loop circuit of the circuit in a close loop feedback system according to the control signal so as to change the circuit performance.

Abstract: An output driver circuit including a pre-driver stage that receives a first data signal, the pre-driver stage including a plurality of first differential pairs that perform current subtraction to output a second data signal based on the first data signal, and an output driver stage electrically coupled to the pre-driver stage that receives the second data signal from the pre-driver stage, the output driver stage including a plurality of second differential pairs that transmit an output signal along transmission lines.

Abstract: An electric power steering apparatus comprises a transmission mechanism for transmitting driving force of a steering assisting electric motor to a steering mechanism. A driven gear of the transmission mechanism is rotatably supported by first and second bearings. One of the first and second bearings includes an inner ring coupled so as to be rotatable together with an output shaft of a steering shaft, an outer ring held on a housing, and a rolling element interposed between the inner ring and the outer ring. One of the inner ring and the outer ring includes an annular elastic plate giving a preload to the rolling element.

Abstract: An equalizer may use reverse scaling of physical dimensions between a plurality of equalizer stages to improve overall bandwidth. The equalizer may provide 20 dB of peaking at 5 GHz with good linearity and little noise accumulation, using CMOS technology.