Patents by Inventor Yoshinori Oda

Yoshinori Oda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230343682
    Abstract: A wire protecting part partially encloses a first lead frame and a second lead frame and has an enclosing surface from which the first and second lead frames protrude. The enclosing surface is parallel to semiconductor chips, and includes a water stop part protruding, from the enclosing surface, between the first and second lead frames.
    Type: Application
    Filed: March 30, 2023
    Publication date: October 26, 2023
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Rikihiro MARUYAMA, Yoshinori ODA, Takahito HARADA
  • Publication number: 20230187320
    Abstract: A semiconductor module includes a semiconductor element, a case configured to house the semiconductor element, and a plurality of control terminal units. Each of the control terminal units includes at least one control terminal electrically connected to the semiconductor element, and a guide block constituted of a separate component from the case fixed integrally to the at least one control terminal. The at least one control terminal each includes a terminal pin part protruding from an outer wall surface of the case. Each of the guide blocks includes a guide pin part protruding from the outer wall surface of the case in a direction the same as the direction in which the terminal pin part protrudes. The guide blocks of the control terminal units are constituted of separate components.
    Type: Application
    Filed: October 28, 2022
    Publication date: June 15, 2023
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Yoshinori ODA, Akira ISO
  • Patent number: 11521941
    Abstract: A semiconductor device including a semiconductor chip disposed on a substrate having a conductive pattern, an insulating plate and a metal plate that are sequentially formed and respectively have the thicknesses of T2, T1 and T3. The metal plate has a plurality of depressions formed on a rear surface thereof. In a side view, a first edge face, which is an edge face of the conductive pattern, is at a first distance away from a second edge face that is an edge face of the metal plate, and a third edge face, which is an edge face of the semiconductor chip, is at a second distance away from the second edge face. Each depression is located within a depression formation distance from the first edge face, where: 0<depression formation distance?(0.9×T12/first distance), and/or (1.1×T12/first distance)?depression formation distance<second distance.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: December 6, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yoshinori Oda, Yoshinori Uezato
  • Publication number: 20220359215
    Abstract: The current disclosure relates to processes for selectively etching material from one surface of a semiconductor substrate over another surface of the semiconductor substrate. The disclosure further relates to assemblies for etching material from a surface of a semiconductor substrate. In the processes, a substrate comprising a first surface and a second surface is provided into a reaction chamber, an etch-priming reactant is provided into the reaction chamber in vapor phase; reactive species generated from plasma are provided into the reaction chamber for selectively etching material from the first surface. The etch-priming reactant is deposited on the first surface and the etch-priming reactant comprises a halogenated hydrocarbon. The halogenated hydrocarbon may comprise a head group and a tail group, and one or both of them may be halogenated.
    Type: Application
    Filed: April 19, 2022
    Publication date: November 10, 2022
    Inventors: René Henricus Jozef Vervuurt, Takayoshi Tsutsumi, Masaru Hori, Nobuyoshi Kobayashi, Yoshinori Oda, Charles Dezelah
  • Publication number: 20210118822
    Abstract: A semiconductor device including a semiconductor chip disposed on a substrate having a conductive pattern, an insulating plate and a metal plate that are sequentially formed and respectively have the thicknesses of T2, T1 and T3. The metal plate has a plurality of depressions formed on a rear surface thereof. In a side view, a first edge face, which is an edge face of the conductive pattern, is at a first distance away from a second edge face that is an edge face of the metal plate, and a third edge face, which is an edge face of the semiconductor chip, is at a second distance away from the second edge face. Each depression is located within a depression formation distance from the first edge face, where: 0<depression formation distance?(0.9×T12/first distance), and/or (1.1×T12/first distance)?depression formation distance<second distance.
    Type: Application
    Filed: December 28, 2020
    Publication date: April 22, 2021
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Yoshinori ODA, Yoshinori UEZATO
  • Patent number: 10137373
    Abstract: An example system includes: a display processing unit performing processing of displaying, on a display, an image concerning a processing result of an application and an operation receiving image for receiving an operation related to the application; a first operation reception unit receiving an operation associated with the operation receiving image by detecting contact with the operation receiving image through the touch panel; a second operation reception unit receiving an operation equivalent to operation associated with the operation receiving image through the operation for the hardware key; and an information processing unit performing information processing concerning the application in response to operation received by the first operation reception unit or the second operation reception unit. The display processing unit makes the operation receiving image non-display in the case where the second operation reception unit receives an operation.
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: November 27, 2018
    Assignee: NINTENDO CO., LTD.
    Inventor: Yoshinori Oda
  • Publication number: 20160059124
    Abstract: An example system includes: a display processing unit performing processing of displaying, on a display, an image concerning a processing result of an application and an operation receiving image for receiving an operation related to the application; a first operation reception unit receiving an operation associated with the operation receiving image by detecting contact with the operation receiving image through the touch panel; a second operation reception unit receiving an operation equivalent to operation associated with the operation receiving image through the operation for the hardware key; and an information processing unit performing information processing concerning the application in response to operation received by the first operation reception unit or the second operation reception unit. The display processing unit makes the operation receiving image non-display in the case where the second operation reception unit receives an operation.
    Type: Application
    Filed: August 6, 2015
    Publication date: March 3, 2016
    Inventor: Yoshinori ODA
  • Patent number: 6818971
    Abstract: A lead frame for a resin-molded semiconductor device is provided with die pads for separately mounting chips of power elements and a control IC thereon; terminal leads arranged in a row at one side and including leads for the die pads, and a main circuit, a control power supply and signal circuit separated from the die pads; and a dam bar connecting the terminal leads. In the main circuit terminals and control power supply terminals, a plurality of leads is formed and drawn in advance. After the lead frame is set in a mold die and is resin-molded, certain leads that are not used as the terminal leads are selected among the plurality of the leads, and the certain leads are cut and removed together with the dam bar.
    Type: Grant
    Filed: January 21, 2003
    Date of Patent: November 16, 2004
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Yoshinori Oda, Atsushi Maruyama
  • Publication number: 20030141579
    Abstract: A lead frame for a resin-molded semiconductor device is provided with die pads for separately mounting chips of power elements and a control IC thereon; terminal leads arranged in a row at one side and including leads for the die pads, and a main circuit, a control power supply and signal circuit separated from the die pads; and a dam bar connecting the terminal leads. In the main circuit terminals and control power supply terminals, a plurality of leads is formed and drawn in advance. After the lead frame is set in a mold die and is resin-molded, certain leads that are not used as the terminal leads are selected among the plurality of the leads, and the certain leads are cut and removed together with the dam bar.
    Type: Application
    Filed: January 21, 2003
    Publication date: July 31, 2003
    Inventors: Yoshinori Oda, Atsushi Maruyama
  • Patent number: 6262902
    Abstract: An intelligent power module (IPM) is formed of an inverter having power elements, a predriver for driving the inverter, and a protect circuit, and all these components are integrated into the same package. A shunt resistor is provided at an output of the inverter so that an end-to-end voltage of the shunt resistor can be output to an external device. This configuration enables an output current from an inverter apparatus incorporating the IPM to be detected without using a current transformer that requires a large installation space. In addition, the module terminals of the IPM and the terminal blocks of the inverter apparatus are integrated together to eliminate the need for wire rods and set screws for connections which are used to connect the module terminals and the terminal blocks together.
    Type: Grant
    Filed: November 23, 1999
    Date of Patent: July 17, 2001
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Manabu Watanabe, Yoshinori Oda