Patents by Inventor Yoshinori Okumura

Yoshinori Okumura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4912535
    Abstract: A semiconductor substrate is formed on its major surface with a first trench and a second trench which is deeper than the first trench. A region held between the first and second trenches serves as a transistor, and impurity regions for serving as source/drain regions are formed on the first and second trench sides. A bit line fills up the first trench and a capacitor electrode fills up the second trench, to be in contact with the impurity regions respectively. A word line is formed on a channel region between the source and drain regions through an oxide film. A semiconductor layer is formed on the major surface of a semiconductor substrate through an oxide film, to be provided with a first trench having the oxide film as a bottom surface and a second trench reaching the semiconductor substrate. The semiconductor layer held between the first and second trenches serves as a transistor, while a bit line and a capacitor electrode fill up the first and second trenches respectively.
    Type: Grant
    Filed: August 8, 1988
    Date of Patent: March 27, 1990
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Yoshinori Okumura
  • Patent number: 4906591
    Abstract: In a method of manufacturing a semiconductor device having an electric contact, semiconductor regions (9) as a source or drain region of a MOS transistor, having a conductivity type opposite to that of a semiconductor substrate (1) are formed selectively on the substrate. An insulating layer (10) is formed on the substrate (1) to expose only a surface of each semiconductor region (9). Impurity ions of the conductivity type opposite to that of the substrate (1) are implanted into the exposed surface of each region (9). After that, a polycrystal silicon layer (13) is formed on the surface of each region (9) implanted with the impurity ions and on the insulating layer (10). Further, impurity ions of the conductivity type opposite to that of the substrate (1) are further implanted into the polycrystal silicon layer (13).
    Type: Grant
    Filed: December 6, 1988
    Date of Patent: March 6, 1990
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Yoshinori Okumura
  • Patent number: 4894695
    Abstract: The semiconductor device in which no stress occurs at the corner portion of the trench comprises a p type semiconductor substrate having a trench and a main surface, a thick insulating film formed on the bottom portion of the trench, a thin insulating film formed on the sidewall portion of the trench and connected to the end portion of the thick insulating film, and an n type impurity region formed in the semiconductor substrate only on the side portion of the thin insulating film.
    Type: Grant
    Filed: March 17, 1988
    Date of Patent: January 16, 1990
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tatsuya Ishii, Yoshinori Okumura, Masao Nagatomo
  • Patent number: 4891327
    Abstract: Impurities of a conductivity type opposite to a semiconductor substrate are ion-implanted utilizing as a mask a resist or the like formed on the major surface of the semiconductor substrate. Impurity regions spaced apart from each other by a predetermined distance are formed by heat treatment. Conductive layers are formed over the respective impurity regions. A conductive material is formed on an exposed semiconductor substrate through an oxide film to cover the conductive layers, and patterned in a predetermined shape. In addition, conductive layers spaced apart form each other by a predetermined distance are formed on the major surface of the semiconductor substrate. Impurities of the conductivity type opposite to that of the semiconductor substrate are ion-implanted into the conductive layers. The impurities included in the conductive layers are diffused into the semiconductor substrate by heat treatment, so that impurity regions spaced apart from each other by a predetermined distance are formed.
    Type: Grant
    Filed: August 3, 1988
    Date of Patent: January 2, 1990
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Yoshinori Okumura
  • Patent number: 4877750
    Abstract: A novel method of fabricating a trench capacitor cell for a semiconductor device is disclosed. The method comprises:forming a trench in a semiconductor substrate;forming a first insulating layer on the side and bottom walls of the trench and forming a first conductor layer on the first insulating layer;filling the trench with a second insulating layer;forming a mask coating over the upper surface of the substrate using a material that can be removed by etching for the first conductor layer;etching selectively the portion of the mask coating over the second insulating layer within the trench;removing the second insulating layer out of the trench;etching the first conductor layer from the bottom of the trench as well as the mask coating; andforming a third insulating layer on the first conductor layer in the trench and fill the trench with a second conductor layer.
    Type: Grant
    Filed: October 7, 1988
    Date of Patent: October 31, 1989
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Yoshinori Okumura
  • Patent number: 4741802
    Abstract: A method for manufacturing a semiconductor device comprises the steps of forming a trench (2) on the major surface of a semiconductor substrate (1) and depositing a polysilicon film (5) on the entire surface of the semiconductor substrate (1) including the inside of said trench (2). In order to form complete isolation in the bottom portion of the trench (2), the trench (2) is filled with an oxide film (10). A refractory metal (12) such as tungsten which can be selectively deposited on polysilicon is deposited only on the polysilicon film (5) on the major surface of the semiconductor substrate (1). The oxide (10) inside the trench (2) removed and then, anisotropic etching of the polysilicon film (5) in the bottom portion of the trench (2) is performed utilizing the refractory metal (12) as a mask, so that isolation is formed in a self-aligning manner. thereafter, an oxide film (13) and a polysilicon film (14) are formed successively, so that three-dimensional charge storage capacitance is achieved.
    Type: Grant
    Filed: May 28, 1987
    Date of Patent: May 3, 1988
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Yoshinori Okumura