Abstract: An improved external semiconductor memory device having a work memory for storing logical address-physical address conversion information.

Abstract: An array of memory cells is physically divided into a data area and a tag area so that respective parts of the two areas share a word line but can be separately erased en bloc. The data area and tag area sharing one word line constitute a single logical unit. In the logical unit, the tag area stores location information for defective memory cells in the corresponding data area. On the basis of this information, the system avoids the use of the defective memory cells. The defective memory cell information is programmed in a test step performed after chip manufacture and, at the same time, ECCs are generated for the defective memory cell information and written to the tag area. Furthermore, the system is informed of the invalidity of the data area that shares a word line with a tag area by writing predetermined data to the tag area. Even when the data area is erased en bloc, the tag area is not erased and the defective memory cell information is retained there.

Abstract: A three-dimensional memory cell, suitable for electrically erasable programmable read only memories (EEPROMS), which has direct-write cell capability is disclosed. The memory cell is utilized in the fabrication of non-volatile, direct-write EEPROM arrays with high integration density. A typical EEPROM array includes a plurality of elongated shallow trenches formed in a semiconductor substrate. Multiple direct-write EEPROM cells are disposed within each elongated trench such that each EEPROM cell shares a recall gate and a program gate with another cell in the same trench. Preferably, a silicon rich dielectric (such as silicon rich oxide) disposed between each floating gate and its associated programming and recall gates. Both common source diffusion and isolated source diffusion embodiments are disclosed. Further, various fabrication methods for the direct-write EEPROM arrays presented are described.

Abstract: A nonvolatile memory-with cluster-erase flash capability. A cluster information sector is included in each of N clusters, the cluster information sector of each cluster being written with the sequence number assigned to the cluster so that no two clusters have the same sequence number. When erasing a given sector, a controller saves its sequence number prior to erasure. Then, when initializing a given erased sector, the controller sets its sequence number to a value greater than the current maximum sequence number. The controller writes user data to sectors other than the cluster information sector for the cluster thus initialized according to their address sequence. Accordingly, an invalid sector can be distinguished from a valid sector without using an overwrite approach.

Abstract: An array of memory cells is physically divided into a data area and a tag area so that respective parts of the two areas share a word line but can be separately erased en bloc. The data area and tag area sharing one word line constitute a single logical unit. In the logical unit, the tag area stores location information for defective memory cells in the corresponding data area. On the basis of this information, the system avoids the use of the defective memory cells. The defective memory cell information is programmed in a test step performed after chip manufacture and, at the same time, ECCs are generated for the defective memory cell information and written to the tag area. Furthermore, the system is informed of the invalidity of the data area that shares a word line with a tag area by writing predetermined data to the tag area. Even when the data area is erased en bloc, the tag area is not erased and the defective memory cell information is retained there.

Abstract: To provide an external storage system using a semiconductor memory in which the data reading and writing between the host CPU can be processed faster than the conventional magnetic disk, and only a particular sector is not frequently written and erased so that the whole memory is effectively used over a long period of time. An address control scheme was introduced in which flexibility is given to the address relation between the host CPU and the external storage and the physical address of the semiconductor memory is not one-sidedly determined by the logical address possessed by the command of the host CPU. Command processing section 34 always prepares memory blocks and sectors for writing or erasing and copying in preparation for the command processing of the host CPU, and records and holds the correspondence relation between the physical address of the selected memory block 32i or sector and the command of the host CPU in address conversion table 36.

Abstract: An array of memory cells is physically divided into a data area and a tag area so that respective parts of the two areas share a word line but can be separately erased en bloc. The data area and tag area sharing one word line constitute a single logical unit. In the logical unit, the tag area stores location information for defective memory cells in the corresponding data area. On the basis of this information, the system avoids the use of the defective memory cells. The defective memory cell information is programmed in a test step performed after chip manufacture and, at the same time, ECCs are generated for the defective memory cell information and written to the tag area. Furthermore, the system is informed of the validity of the data area that shares a word line with a tag area by writing predetermined data to the tag area. Even when the data area is erased en bloc, the tag area is not erased and the defective memory cell information is retained there.

Abstract: A three-dimensional memory cell, suitable for electrically erasable programmable read only memories (EEPROMS), which has direct-write cell capability is disclosed. The memory cell is utilized in the fabrication of non-volatile, direct-write EEPROM arrays with high integration density. A typical EEPROM array includes a plurality of elongated shallow trenches formed in a semiconductor substrate. Multiple direct-write EEPROM cells are disposed within each elongated trench such that each EEPROM cell shares a recall gate and a program gate with another cell in the same trench. Preferably, a silicon rich dielectric (such as silicon rich oxide) disposed between each floating gate and its associated programming and recall gates. Both common source diffusion and isolated source diffusion embodiments are disclosed. Further, various fabrication methods for the direct-write EEPROM arrays presented are described.

Abstract: A three-dimensional memory cell, suitable for electrically erasable programmable read only memories (EEPROMS), which has direct-write cell capability is disclosed. The memory cell is utilized in the fabrication of non-volatile, direct-write EEPROM arrays with high integration density. A typical EEPROM array includes a plurality of elongated shallow trenches formed in a semiconductor substrate. Multiple direct-write EEPROM cells are disposed within each elongated trench such that each EEPROM cell shares a recall gate and a program gate with another cell in the same trench. Preferably, a silicon rich dielectric (such as silicon rich oxide) disposed between each floating gate and its associated programming and recall gates. Both common source diffusion and isolated source diffusion embodiments are disclosed. Further, various fabrication methods for the direct-write EEPROM arrays presented are described.

Abstract: A nonvolatile memory with cluster-erase flash capability. A cluster information sector is included in each of N clusters, the cluster information sector of each cluster being written with the sequence number assigned to the cluster so that no two clusters have the same sequence number. When erasing a given sector, a controller saves its sequence number prior to erasure. Then, when initializing a given erased sector, the controller sets its sequence number to a value greater than the current maximum sequence number. The controller writes user data to sectors other than the cluster information sector for the cluster thus initialized according to their address sequence. Accordingly, an invalid sector can be distinguished from a valid sector without using an overwrite approach.

Abstract: To achieve high speed line-thinning, an electronic picture to be processed is divided into sections, and the scanning for line-thinning is performed for each section. If no point removal is performed in the scanning of a section, the line-thinning is completed for that section. When points are removed in the scanning, incomplete areas that require further line-thinning are determined based on positions where the points are removed. In the next scanning, scanning for line-thinning is not performed for all of the sections, but is done for areas within sections that contain the incomplete areas. These areas are smaller than the sections and are variably determined according to the size of their incomplete area. Thus, the area to be scanned is reduced and dynamically controlled. It is because the incomplete areas become smaller and smaller as the scanning is repeated, that the area variably determined according to the size of the incomplete area also becomes smaller.

Abstract: A sheet presser mechanism for use in a recorder comprises a platen rotatable about its own axis, a drawing instrument directed toward the platen and movable axially thereof, a pair of spaced support members movable toward and away from the platen, a pair of presser roller units rotatably supported on the support members, respectively, and positioned respectively at axial ends of the platen. The presser rollers have shafts parallel to the platen and normally held resiliently against the platen, and a paper presser bar is spaced from the presser rollers in a circumferential direction of the platen so as to extend parallel to the platen. A pivot lever with a cover thereon supports the paper presser bar for moving the latter away from the platen, and a pair of presser members are actuatable in response to turning movement of the pivot lever to move the paper presser bar away from the platen for pushing the support members to move the presser rollers away from the platen.

Abstract: A sheet pressing mechanism in a pen type recording device including a rotatable platen and a pen adapted to move in the axial direction of the platen while contacting the platen, in which pressure rollers are brought into contact with outer peripheral surfaces of end portions of the platen, the pressure rollers being rotatably mounted on a support shaft extending in parallel with the axis of the platen, and in which the said outer peripheral surfaces of the end portions of the platen are formed of a soft material capable of being depressed by the contact pressure of the pressure rollers.

Abstract: A multi-color pen recorder comprises a platen rotatable about its own axis, a pen carriage mounted on the platen and movable axially therealong, a pen holder removably mounted on the pen carriage for removably supporting a plurality of pens on the pen holder, and a hammer mounted on the pen carriage for pushing one of the pens in a position on the pen holder toward the platen.

Abstract: A sheet guide mechanism in a recording device including a rotatable platen and a recording member opposed to the platen, comprising pressure rollers adapted to come into pressure contact with the platen for pressing down a recording sheet, and a guide plate extending from a lower portion of a recording side of the platen in a direction opposite to the recording side past below the platen, the guide plate having windows formed therein for avoiding the pressure rollers and guide pieces formed on edges in a sheet inserting direction of the windows, the guide pieces being bent in a direction away from the platen.