Abstract: The serial communication system includes a first communication device and a second communication device connected with the first communication device. The first communication device and the second communication device respectively operates in response to a first clock signal and a second clock. The first communication device generates a first training signal, transmits the first training signal to the second communication device, encodes a first data signal to generate a first encoded signal, and transmits the first encoded signal to the second communication device. The second communication device measures a second interval length, receives the first encoded signal from the first communication device, and decodes the first data signal from the first encoded signal by detecting the level of the first encoded signal at a preset first point of time preset and a preset second point of time.

Abstract: The serial communication system includes a first communication device and a second communication device connected with the first communication device. The first communication device and the second communication device respectively operates in response to a first clock signal and a second clock. The first communication device generates a first training signal, transmits the first training signal to the second communication device, encodes a first data signal to generate a first encoded signal, and transmits the first encoded signal to the second communication device. The second communication device measures a second interval length, receives the first encoded signal from the first communication device, and decodes the first data signal from the first encoded signal by detecting the level of the first encoded signal at a preset first point of time preset and a preset second point of time.

Abstract: A transmission interval counter measures the period of a packet sync generated in a sync generator. A comparator compares the period of the packet sync to a reference interval as selected by a type selector to calculate a period error. A correction value calculator calculates a correction value based on the period error. An adder sums the correction value to a predetermined value to output a sum. A frequency dividing counter counts the high-speed clock signals to output its count, and is reset by a pulse. A comparator outputs the pulse when the count coincides with the sum. A circuit generates clocks synchronized with the pulses. A circuit frequency-divides the clocks by ? to generate synchronization signals.

Abstract: In this clock control circuit and this clock control method, during a standby-mode of a CPU, a low-speed clock is supplied. Processings including timer processing and receiving processing are carried out by low-speed operation at the CPU. When an interrupt signal is inputted to the CPU which is in the standby mode, a high-speed clock source is activated, and counting of the low-speed clock is started at a counter. When a count value of the counter reaches a set value of a register, a high-speed clock is selected by a selection signal. The high-speed clock is supplied to the CPU, and interruption processing is started.

Abstract: The synchronization signal generating section generates a packet synchronization signal PSYNC such that it is synchronized with the cycle of packets received from the master device. The interface control section generates a transfer clock PCMCLK used in transferring the data in the packets, from the internal clock. The interface control section measures the cycle of the packet synchronization signal PSYNC, and if the actual cycle of PSYNC is longer than the designated value, it makes the cycle of the transfer clock corresponding to the last data element in the packet longer than the cycle of the transfer clock corresponding to the other data elements, whereas if the actual cycle of PSYNC is shorter than the designated value, it makes the cycle of the transfer clock corresponding to the last data element in the packet shorter than the cycle of the transfer clock corresponding to the other data elements.

Abstract: In this clock control circuit and this clock control method, during a standby-mode of a CPU, a low-speed clock is supplied. Processings including timer processing and receiving processing are carried out by low-speed operation at the CPU. When an interrupt signal is inputted to the CPU which is in the standby mode, a high-speed clock source is activated, and counting of the low-speed clock is started at a counter. When a count value of the counter reaches a set value of a register, a high-speed clock is selected by a selection signal. The high-speed clock is supplied to the CPU, and interruption processing is started.

Abstract: A noise reduction circuit suppressing noise ascribable to a bit error to prevent the data quality from being lowered includes a data storage storing input data chronologically continuously supplied. The data storage includes three data registers connected in tandem to each other. The noise detector detects the magnitude of the noise, using three pieces of data respectively supplied from the three data registers to feed an output selector with an output selection signal, selecting noise correction or non-correction, depending on the comparison of the magnitude of the detected noise with a preset threshold. The output selector outputs either one of the inherent input data to be output and correction data calculated by a correction value calculator, depending on the output selection signal, to perform correction on the noise larger than the threshold value.

Abstract: A transmission interval counter measures the period of a packet sync generated in a sync generator. A comparator compares the period of the packet sync to a reference interval as selected by a type selector to calculate a period error. A correction value calculator calculates a correction value based on the period error. An adder sums the correction value to a predetermined value to output a sum. A frequency dividing counter counts the high-speed clock signals to output its count, and is reset by a pulse. A comparator outputs the pulse when the count coincides with the sum. A PCMCLK circuit generates clocks (PCMCLK) synchronized with the pulses. A PCMSYNC circuit frequency-divides the clocks (PCMCLK) by ⅛ to generate synchronization signals (PCMSYNC).

Abstract: After a pseudo synchronizing information is detected and a synchronization is lost, an arithmetic operation unit adds a random number outputted from a random number generator to a frame length information calculated. The detection of a synchronizing information is again executed in a stream counter to a bit stream of a plurality of continuous transmission data, from a bit located in delay for the bit of output information being a calculation result by the arithmetic operation unit. The frame synchronous circuit thus constructed achieves a synchronization setup securely in a high speed, if a transmission data containing a pseudo synchronizing information is transmitted.

Abstract: The synchronization signal generating section generates a packet synchronization signal PSYNC such that it is synchronized with the cycle of packets received from the master device. The interface control section generates a transfer clock PCMCLK used in transferring the data in the packets, from the internal clock. The interface control section measures the cycle of the packet synchronization signal PSYNC, and if the actual cycle of PSYNC is longer than the designated value, it makes the cycle of the transfer clock corresponding to the last data element in the packet longer than the cycle of the transfer clock corresponding to the other data elements, whereas if the actual cycle of PSYNC is shorter than the designated value, it makes the cycle of the transfer clock corresponding to the last data element in the packet shorter than the cycle of the transfer clock corresponding to the other data elements.