Patents by Inventor Yoshinori Shizuno
Yoshinori Shizuno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9893016Abstract: A multilayer wiring board includes a main wiring board including insulation layers, first via conductors formed in the insulation layers, and a first conductive layer including first mounting pads such that the first mounting pads are positioned to mount a first electronic component and a second electronic component adjacent to each other on the main wiring board, and a wiring structure body mounted on the main wiring board such that the wiring structure body is positioned in an outermost insulation layer of the insulation layers, the wiring structure body including a second conductive layer which includes second mounting pads such that the second mounting pads are positioned to connect to the first electronic component and the second electronic component mounted on the main wiring board. The first via conductors are formed such that the first via conductors have diameters which increase in a same direction.Type: GrantFiled: October 12, 2015Date of Patent: February 13, 2018Assignee: IBIDEN CO., LTD.Inventors: Hajime Sakamoto, Yoshinori Shizuno, Shigeru Yamada, Takashi Kariya
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Patent number: 9480157Abstract: A wiring board includes a first interlayer insulation layer, a second interlayer insulation layer formed on the first interlayer insulation layer and having an opening portion, first conductive pads formed on the second interlayer insulation layer, a conductive plane layer formed on the first interlayer insulation layer such that the conductive plane layer is exposed by the opening portion of the second interlayer insulation layer, a wiring structure positioned directly on the conductive plane layer such that the wiring structure is accommodated in the opening portion of the second interlayer insulation layer, and second conductive pads formed on the wiring structure such that the first conductive pads and the second conductive pads are set to be positioned on a same plane.Type: GrantFiled: April 7, 2015Date of Patent: October 25, 2016Assignee: IBIDEN CO., LTD.Inventors: Yoshinori Shizuno, Nobuya Takahashi, Hisayuki Nakagome, Asuka Ii
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Patent number: 9433085Abstract: An electronic component includes an insulation layer, an alignment mark positioned on a first surface of the insulation layer, and an adhesive layer including an optically opaque agent and formed on the first surface of the insulation layer or a second surface of the insulation layer on the opposite side with respect to the first surface of the insulation layer. The adhesive layer has an opening portion formed at the position corresponding to the alignment mark such that the opening portion exposes the alignment mark directly or through the insulation layer.Type: GrantFiled: April 23, 2014Date of Patent: August 30, 2016Assignee: IBIDEN CO., LTD.Inventors: Yoshinori Shizuno, Makoto Terui, Masatoshi Kunieda, Asuka Ii
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Patent number: 9431347Abstract: A wiring board includes a first insulation layer, first conductive patterns formed on the first insulation layer and including first mounting pads positioned to mount a semiconductor element, a wiring structure positioned in the first insulation layer and having a second insulation layer, second conductive patterns formed on the second insulation layer, and second mounting pads connected to the second conductive patterns, and third mounting pads formed on the first insulation layer above the second mounting pads and connected to the second mounting pads such that the third mounting pads are positioned to mount the semiconductor element and form a distance between adjacent first and third mounting pads which is greater than a distance between adjacent first mounting pads.Type: GrantFiled: June 3, 2014Date of Patent: August 30, 2016Assignee: IBIDEN CO., LTD.Inventors: Masatoshi Kunieda, Makoto Terui, Asuka Il, Yoshinori Shizuno
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Patent number: 9425159Abstract: A wiring board includes a first insulation layer, first conductive patterns formed on the first insulation layer and including first mounting pads positioned to mount a semiconductor element, a wiring structure positioned in the first insulation layer and including a second insulation layer, second conductive patterns formed on the second insulation layer, and second mounting pads connected to the second conductive patterns, and third mounting pads formed on the first insulation layer above the second mounting pads and connected to the second mounting pads such that the third mounting pads are positioned to mount the semiconductor element and are set off from the second mounting pads toward the semiconductor element.Type: GrantFiled: June 3, 2014Date of Patent: August 23, 2016Assignee: IBIDEN CO., LTD.Inventors: Makoto Terui, Masatoshi Kunieda, Yoshinori Shizuno, Asuka Il
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Publication number: 20160105960Abstract: A multilayer wiring board includes a main wiring board including insulation layers, first via conductors formed in the insulation layers, and a first conductive layer including first mounting pads such that the first mounting pads are positioned to mount a first electronic component and a second electronic component adjacent to each other on the main wiring board, and a wiring structure body mounted on the main wiring board such that the wiring structure body is positioned in an outermost insulation layer of the insulation layers, the wiring structure body including a second conductive layer which includes second mounting pads such that the second mounting pads are positioned to connect to the first electronic component and the second electronic component mounted on the main wiring board. The first via conductors are formed such that the first via conductors have diameters which increase in a same direction.Type: ApplicationFiled: October 12, 2015Publication date: April 14, 2016Applicant: IBIDEN CO., LTD.Inventors: Hajime SAKAMOTO, Yoshinori SHIZUNO, Shigeru YAMADA, Takashi KARIYA
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Publication number: 20150216049Abstract: A wiring board includes a first interlayer insulation layer, a second interlayer insulation layer formed on the first interlayer insulation layer and having an opening portion, first conductive pads formed on the second interlayer insulation layer, a conductive plane layer formed on the first interlayer insulation layer such that the conductive plane layer is exposed by the opening portion of the second interlayer insulation layer, a wiring structure positioned directly on the conductive plane layer such that the wiring structure is accommodated in the opening portion of the second interlayer insulation layer, and second conductive pads formed on the wiring structure such that the first conductive pads and the second conductive pads are set to be positioned on a same plane.Type: ApplicationFiled: April 7, 2015Publication date: July 30, 2015Applicant: IBIDEN CO., LTD.Inventors: Yoshinori SHIZUNO, Nobuya TAKAHASHI, Hisayuki NAKAGOME, Asuka II
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Patent number: 9035463Abstract: A wiring board includes a first insulation layer, a first conducive layer having first conductive patterns formed on the first insulation layer, a wiring structure positioned on the first insulation layer and including a second insulation layer and a second conductive layer having second conductive patterns formed on the second insulation layer, multiple conductive patterns formed on the wiring structures such that the conductive patterns are connected to the second conductive patterns, respectively, multiple first electrodes formed on the first conductive patterns, respectively, and multiple second electrodes formed on the conductive patterns connected to the second conductive patterns of the wiring structure, respectively. The first electrodes and the second electrodes have top surfaces which form the same plane.Type: GrantFiled: May 16, 2013Date of Patent: May 19, 2015Assignee: IBIDEN CO., LTD.Inventors: Yoshinori Shizuno, Nobuya Takahashi, Hisayuki Nakagome, Asuka Ii
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Publication number: 20150060127Abstract: A combined printed wiring board includes a multilayer printed wiring board, and a wiring film fixed to a surface of the multilayer printed wiring board and including a first wiring structure formed to connect multiple semiconductor elements and a second wiring structure formed to connect the multilayer printed wiring board and each of the semiconductor elements.Type: ApplicationFiled: August 29, 2014Publication date: March 5, 2015Applicant: IBIDEN CO., LTD.Inventors: Makoto Terui, Takashi Kariya, Yoshinori Shizuno, Masatoshi Kunieda
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Publication number: 20150060124Abstract: A combined printed wiring board includes a multilayer printed wiring board having an outermost insulation layer, and a wiring film fixed to a portion of the outermost insulation layer of the multilayer printed wiring board. The wiring film includes dense-pitch pads formed on a semiconductor-mounting surface of the wiring film, the multilayer printed wiring board has sparse-pitch pads formed on a semiconductor-mounting surface of the multilayer printed wiring board, the dense-pitch pads are formed to facilitate electrical connection between a first semiconductor element and a second semiconductor element, and the sparse-pitch pads are formed to facilitate electrical connection between the multilayer printed wiring board and the first semiconductor element and/or the second semiconductor element.Type: ApplicationFiled: August 29, 2014Publication date: March 5, 2015Applicant: IBIDEN CO., LTD.Inventors: Makoto TERUI, Takashi KARIYA, Yoshinori SHIZUNO, Masatoshi KUNIEDA
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Publication number: 20140360767Abstract: A wiring board includes a first insulation layer, first conductive patterns formed on the first insulation layer and including first mounting pads positioned to mount a semiconductor element, a wiring structure positioned in the first insulation layer and including a second insulation layer, second conductive patterns formed on the second insulation layer, and second mounting pads connected to the second conductive patterns, and third mounting pads formed on the first insulation layer above the second mounting pads and connected to the second mounting pads such that the third mounting pads are positioned to mount the semiconductor element and are set off from the second mounting pads toward the semiconductor element.Type: ApplicationFiled: June 3, 2014Publication date: December 11, 2014Applicant: IBIDEN CO., LTD.Inventors: Makoto TERUI, Masatoshi KUNIEDA, Yoshinori SHIZUNO, Asuka Il
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Publication number: 20140360759Abstract: A wiring board includes a first insulation layer, first conductive patterns formed on the first insulation layer and including first mounting pads positioned to mount a semiconductor element, a wiring structure positioned in the first insulation layer and having a second insulation layer, second conductive patterns formed on the second insulation layer, and second mounting pads connected to the second conductive patterns, and third mounting pads formed on the first insulation layer above the second mounting pads and connected to the second mounting pads such that the third mounting pads are positioned to mount the semiconductor element and form a distance between adjacent first and third mounting pads which is greater than a distance between adjacent first mounting pads.Type: ApplicationFiled: June 3, 2014Publication date: December 11, 2014Applicant: IBIDEN CO., LTD.Inventors: Masatoshi Kunieda, Makoto Terui, Asuka Il, Yoshinori Shizuno
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Publication number: 20140347837Abstract: A wiring board includes multiple insulation layers including an outermost insulation layer, a first conductive pattern formed between the insulation layers, a wiring structure positioned in the outermost insulation layer and having multiple first pads such that the first pads are positioned to connect multiple terminals of a first electronic component, respectively, and multiple second pads formed on the outermost insulation layer such that the second pads are positioned to connect terminals of a second electronic component, respectively, and are set at intervals which are greater than intervals of the first pads.Type: ApplicationFiled: May 21, 2014Publication date: November 27, 2014Applicant: IBIDEN CO., LTD.Inventors: Takashi KARIYA, Yoshinori Shizuno, Makoto Terui, Masatoshi Kunieda
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Publication number: 20140311780Abstract: An electronic component includes an insulation layer, an alignment mark positioned on a first surface of the insulation layer, and an adhesive layer including an optically opaque agent and formed on the first surface of the insulation layer or a second surface of the insulation layer on the opposite side with respect to the first surface of the insulation layer. The adhesive layer has an opening portion formed at the position corresponding to the alignment mark such that the opening portion exposes the alignment mark directly or through the insulation layer.Type: ApplicationFiled: April 23, 2014Publication date: October 23, 2014Applicant: IBIDEN CO., LTD.Inventors: Yoshinori SHIZUNO, Makoto TERUI, Masatoshi KUNIEDA, Asuka Il
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Publication number: 20140231990Abstract: A semiconductor device includes a semiconductor chip and a wiring board formed on the semiconductor chip. The wiring board includes a first insulation layer, first conductive patterns on the first layer, first via conductors formed in the first layer and connecting the first patterns and electrode pads of the chip, respectively, a second insulation layer on the first layer, second conductive patterns on the second layer, and second via conductors formed in the second layer and connecting the first conductive patterns and the second patterns, respectively, each second via conductors has a side surface extending through the second layer such that the side surface has a bent portion which changes inclination of the side surface in depth direction of each second via conductor, and the second patterns are positioned to fan in or out with respect to the electrode pads.Type: ApplicationFiled: April 30, 2014Publication date: August 21, 2014Applicant: IBIDEN CO., LTD.Inventors: Shinji OUCHI, Shigeru YAMADA, Makoto TERUI, Yoshinori SHIZUNO
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Publication number: 20140231947Abstract: A semiconductor module including a semiconductor chip having a light receiving device formed at a front thereof and light permeable cover having a front, a back, and a side. The light permeable cover is disposed opposite to the front of the semiconductor chip such that the front of the semiconductor chip is covered by the back of the light permeable cover. The permeable cover is provided at the outer circumferential region of the front thereof and at the side thereof with a light shielding layer. It is possible to prevent the incidence of unnecessary light from the side of the light permeable cover of a CSP and to easily adjust the distance between a lens and the front of the semiconductor chip within tolerance.Type: ApplicationFiled: April 24, 2014Publication date: August 21, 2014Applicant: LAPIS Semiconductor Co., Ltd.Inventor: Yoshinori SHIZUNO
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Patent number: 8759691Abstract: A wiring board has a first resin insulation layer, a first conductive pattern formed on the first resin insulation layer, a second resin insulation layer formed on the first conductive pattern and having an opening portion exposing at least a portion of the first conductive pattern, a second conductive pattern formed on the second resin insulation layer, and a via conductor formed in the opening portion of the second resin insulation layer and electrically connecting the first conductive pattern and the second conductive pattern. The via conductor has a side surface extending between the first conductive pattern and the second conductive pattern and a bent portion where an inclination of the side surface of the via conductor changes in a depth direction of the via conductor.Type: GrantFiled: July 1, 2011Date of Patent: June 24, 2014Assignee: Ibiden Co., Ltd.Inventors: Shinji Ouchi, Shigeru Yamada, Makoto Terui, Yoshinori Shizuno
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Patent number: 8755196Abstract: A wiring board including a first insulation layer, a conductive pattern formed on the first insulation layer, a second insulation layer formed on the conductive pattern and the first insulation layer and having an opening portion exposing at least a portion of the conductive pattern, and a connection conductor formed in the opening portion of the second insulation layer such that the connection conductor is positioned on the portion of the conductive pattern. The connection conductor has a tip portion which protrudes from a surface of the second insulation layer and which has a tapered side surface tapering toward an end of the tip portion.Type: GrantFiled: July 1, 2011Date of Patent: June 17, 2014Assignee: Ibiden Co., Ltd.Inventors: Shinji Ouchi, Shigeru Yamada, Makoto Terui, Yoshinori Shizuno
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Patent number: 8742323Abstract: A semiconductor module including a semiconductor chip having a light receiving device formed at a front thereof and a light permeable cover having a front, a back, and a side. The light permeable cover is disposed opposite to the front of the semiconductor chip such that the front of the semiconductor chip is covered by the back of the light permeable cover. The light permeable cover is provided at the outer circumferential region of the front thereof and at the side thereof with a light shielding layer. It is possible to prevent the incidence of unnecessary light from the side of the light permeable cover of a CSP and to easily adjust the distance between a lens and the front of the semiconductor chip within tolerance.Type: GrantFiled: November 6, 2009Date of Patent: June 3, 2014Assignee: LAPIS Semiconductor Co., Ltd.Inventor: Yoshinori Shizuno
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Publication number: 20140102768Abstract: A wiring board includes a first insulation layer, a first conductive pattern structure formed on the first insulation layer, a wiring structure formed on the first insulation layer and including a second insulation layer and a second conductive pattern structure on the second insulation layer, and a third insulation layer formed on the first insulation layer and the first conductive pattern structure and having first and second openings such that the first opening is exposing at least a portion of a surface of the wiring structure and the second opening is exposing at least a portion of the first conductive pattern structure. The wiring structure includes a third conductive pattern structure forming an outermost layer of the wiring structure and including a mounting pad structure which mounts a semiconductor device. The first opening is formed such that the first opening is exposing pad formation area of the mounting pad structure.Type: ApplicationFiled: October 15, 2013Publication date: April 17, 2014Applicant: IBIDEN CO., LTD.Inventors: Yoshinori SHIZUNO, Makoto Terui, Masatoshi Kunieda, Takashi Kariya