Abstract: An information processing device includes: a memory; a processor coupled to the memory and configured to: perform, based on input descriptions of a first circuit module that performs a first task and a second circuit module that receive data output from the first circuit module and performs a second task, high-level synthesis of the first circuit module and the second circuit module; synthesize an interface circuit that includes a memory that performs data transfer between the circuit modules based on write information of the data and read information of the data; calculate a minimum operation start interval of the interface circuit based on the write information of the data and the read information of the data; and provide, when the calculated minimum operation start interval is larger than a minimum operation start intervals of the first circuit module and the second circuit module, a storage element in the interface circuit.

Abstract: A non-transitory computer-readable storage medium storing a program that causes a processor included in an apparatus to execute a process. The process includes specifying a first moving distance in which each of the plurality of mobile objects moves from one task to another task for each of multiple task pairs, based on layout information expressing a movement route in which a plurality of mobile objects is movable in, initial position information indicating an initial position of the plurality of mobile objects, and task information indicating a start position and an end position of a plurality of tasks, specifying a second moving distance of the plurality of mobile objects from the start position to the end position for the plurality of tasks, based on the layout information and the task information, and generating, based on the first moving distance and the second moving distance, an evaluation function of an Ising model.

Abstract: An optimization apparatus, includes a memory; and a processor coupled to the memory and the processor configured to: compute a provisional optimum solution of a combinatorial optimization problem by searching a ground state for an Ising model acquired by converting the combinatorial optimization problem, execute a simulation using the provisional optimum solution, evaluate a result of the simulation based on an evaluation criterion value representing an evaluation criterion for the result of the simulation, when the result satisfies the evaluation criterion, output the provisional optimum solution as an optimum solution, and when the result does not satisfy the evaluation criterion, generate an updated Ising model acquired by adding a first constraint term based on the result to the Ising model and execute a search for a ground state for the updated Ising model.

Abstract: A regenerative braking control apparatus equipped on an electrically driven vehicle having road wheels and an electric motor for driving the road wheels for running. An operation unit is provided for the driver of the vehicle to select a magnitude of the braking force to be generated by the electric motor during regenerative braking. A determination unit determines, on the basis of conditions of the electrically driven vehicle, whether or not a selected braking force selected through the operation unit is acceptable. A notifier unit is constructed such that, in a case where the selected braking force is determined to be unacceptable by the determination unit, the notifier unit provides a corresponding notification to the driver.

Abstract: An information processing device includes: a memory; a processor coupled to the memory and configured to: perform, based on input descriptions of a first circuit module that performs a first task and a second circuit module that receive data output from the first circuit module and performs a second task, high-level synthesis of the first circuit module and the second circuit module; synthesize an interface circuit that includes a memory that performs data transfer between the circuit modules based on write information of the data and read information of the data; calculate a minimum operation start interval of the interface circuit based on the write information of the data and the read information of the data; and provide, when the calculated minimum operation start interval is larger than a minimum operation start intervals of the first circuit module and the second circuit module, a storage element in the interface circuit.

Abstract: Provided is a regenerative coordination brake control device that reduces the frequency of switching regenerative braking between a restricted state, in which regenerative braking is prohibited or suppressed, and a restriction removed state, in which the restriction on regenerative braking is removed. A regenerative coordination brake control device 91 includes a regeneration restriction condition determiner 92, which outputs a regeneration restriction signal Si when determining that a restriction condition for prohibiting or suppressing regenerative braking is met, an acceleration operation detector 93, which outputs a regeneration restriction removal signal S2 when detecting an acceleration of the vehicle, and a regeneration restriction removal determiner 94, which determines whether a restriction on regenerative braking of the vehicle that is in the restricted state is to be continuously imposed or removed using the regeneration restriction removal signal S2 and the regeneration restriction signal S1.

Abstract: An information processing apparatus includes a memory, and a processor coupled to the memory, wherein the processor is configured to acquire, by analyzing a program, a first address of the memory at which a memory access instruction in the program is stored, and a second address of the memory to be accessed by the memory access instruction, and generate first information indicating a correspondence between the first address and the second address.

Abstract: A method, performed by a computer for controlling a communication path among a plurality of processing units, includes: executing an acquiring process that includes acquiring communication cost of communication paths among the plurality of processing units; and executing an adding control process that includes performing control to add a bypass communication path which connects a first processing unit and a second processing unit, each of the first and second processing unit being any of the plurality of processing units, and the communication cost of a communication path between the first and second processing units being higher than a first threshold value.

Abstract: Provided is a regenerative coordination brake control device that reduces the frequency of switching regenerative braking between a restricted state, in which regenerative braking is prohibited or suppressed, and a restriction removed state, in which the restriction on regenerative braking is removed. A regenerative coordination brake control device 91 includes a regeneration restriction condition determiner 92, which outputs a regeneration restriction signal S1 when determining that a restriction condition for prohibiting or suppressing regenerative braking is met, an acceleration operation detector 93, which outputs a regeneration restriction removal signal S2 when detecting an acceleration of the vehicle, and a regeneration restriction removal determiner 94, which determines whether a restriction on regenerative braking of the vehicle that is in the restricted state is to be continuously imposed or removed using the regeneration restriction removal signal S2 and the regeneration restriction signal S1.

Abstract: A regenerative braking control apparatus equipped on an electrically driven vehicle having road wheels and an electric motor for driving the road wheels for running. An operation unit is provided for the driver of the vehicle to select a magnitude of the braking force to be generated by the electric motor during regenerative braking. A determination unit determines, on the basis of conditions of the electrically driven vehicle, whether or not a selected braking force selected through the operation unit is acceptable. A notifier unit is constructed such that, in a case where the selected braking force is determined to be unacceptable by the determination unit, the notifier unit provides a corresponding notification to the driver.

Abstract: A control device for controlling an electric vehicle includes a driving source that rotates wheels, a braking device that applies braking force to the wheels, a creep torque control portion that controls magnitude of creep torque to be applied to the wheels, wherein the creep torque control portion includes a braking force detecting unit that detects the braking force applied by the braking device, a fundamental creep torque calculating unit that calculates fundamental creep torque corresponding to vehicle speed, a creep suppression torque calculating unit that calculates creep suppression torque smaller than the fundamental creep torque based on a result of the detection of the braking force detecting unit and a creep torque calculating unit that calculate the creep torque by subtracting the creep suppression torque from the fundamental creep torque.

Abstract: A circuit includes don't-care a code-value calculation circuit to calculate third code-values by coding a signal sequence in accordance with a coding scheme; a first sequence-detection circuit to detect a first sequence based on comparison of a first code-value with a difference between the current third code-value and a fourth code-value that is the third code-value preceding the current third code-value by a length of the first sequence; an expected-value calculation circuit to calculate an expected value of the third code-value at the end of the third sequence based on a second code-value and a fifth code-value that is one of the third code-values; and a determination circuit to detect the end of the second sequence based on a length of a fourth sequence, notify an expected-value calculation circuit of the detection of the second sequence, and output a detection signal indicating detection of a detection-target sequence.

Abstract: A control device for controlling an electric vehicle includes a driving source that rotates wheels, a braking device that applies braking force to the wheels, a creep torque control portion that controls magnitude of creep torque to be applied to the wheels, wherein the creep torque control portion includes a braking force detecting unit that detects the braking force applied by the braking device, a fundamental creep torque calculating unit that calculates fundamental creep torque corresponding to vehicle speed, a creep suppression torque calculating unit that calculates creep suppression torque smaller than the fundamental creep torque based on a result of the detection of the braking force detecting unit and a creep torque calculating unit that calculate the creep torque by subtracting the creep suppression torque from the fundamental creep torque.

Abstract: Memories retain data blocks on which exclusive logical OR computation is performed, and selection circuits receive a selection signal and select two or more data blocks for use in exclusive logical OR computation from among a plurality of data blocks read from the memories on the basis of the selection signal, and XOR circuits (exclusive logical OR computation circuits) perform exclusive logical OR computation based on the two or more data blocks selected by the selection circuits.

Abstract: A circuit design support apparatus acquires an encoding matrix and information indicative of a start timing. For each timing after the start timing indicated by the acquired information, among the timings corresponding to column vectors of the encoding matrix, the circuit design support apparatus identifies among first partial data stored in BRAMs, a first partial data overwritten by a second partial data at the timing. For each of the timings after the start timing, the circuit design support apparatus identifies an XOR operation based on the identified first partial data among multiple XOR operations. For each of the timings after the start timing, the circuit design support apparatus identifies among timings before the start timing included in the timings, a timing having the same operation result of the identified XOR operation as the operation result of the identified XOR operation based on the vector corresponding to the timing.

Abstract: A circuit includes don't-care a code-value calculation circuit to calculate third code-values by coding a signal sequence in accordance with a coding scheme; a first sequence-detection circuit to detect a first sequence based on comparison of a first code-value with a difference between the current third code-value and a fourth code-value that is the third code-value preceding the current third code-value by a length of the first sequence; an expected-value calculation circuit to calculate an expected value of the third code-value at the end of the third sequence based on a second code-value and a fifth code-value that is one of the third code-values; and a determination circuit to detect the end of the second sequence based on a length of a fourth sequence, notify an expected-value calculation circuit of the detection of the second sequence, and output a detection signal indicating detection of a detection-target sequence.

Abstract: A behavioral synthesis method includes: expanding, by a computer, loop processing included in a behavioral description; extracting a part at which same processing is executed from an expanded loop processing; transforming the behavioral description by turning the part to a function; and carrying out behavioral synthesis based on a transformed behavioral description.

Abstract: A semiconductor memory includes a memory cell array that includes data cells of x bits and redundant cells of y bits for each word; a position-data storage unit that stores, for each word, defective-cell position data of defective cells of the data cells and the redundant cells; and a read circuit that reads data from cells of x bits based on the defective-cell position data stored in the position-data storage unit for a specified word of which address is specified as read address, the cells of x bits being formed by the data cells of x bits and the redundant cells of y bits of the specified word other than the defective cells.

Abstract: A semiconductor memory includes a memory cell array that includes data cells of x bits and redundant cells of y bits for each word; a position-data storage unit that stores, for each word, defective-cell position data of defective cells of the data cells and the redundant cells; and a read circuit that reads data from cells of x bits based on the defective-cell position data stored in the position-data storage unit for a specified word of which address is specified as read address, the cells of x bits being formed by the data cells of x bits and the redundant cells of y bits of the specified word other than the defective cells.

Abstract: A semiconductor memory includes a memory cell array that includes data cells of x bits and redundant cells of y bits for each word; a position-data storage unit that stores, for each word, defective-cell position data of defective cells of the data cells and the redundant cells; and a read circuit that reads data from cells of x bits based on the defective-cell position data stored in the position-data storage unit for a specified word of which address is specified as read address, the cells of x bits being formed by the data cells of x bits and the redundant cells of y bits of the specified word other than the defective cells.