Abstract: A diskarray system has a diskarray controller and a plurality of disk devices. Each of the disk devices has a media, a head, and a head position controller. The diskarray controller performs online data check operation, and stops the online data check operation over the disk device at first predetermined timing. After stopping the online data check operation, the diskarray controller issues an unload enable command to the disk device so as to move the head to a position different from positions at which the head reads or writes data from or to the media. The head position controller of the disk device moves the position of the head on the basis of the received unload enable command.

Abstract: A diskarray system has a diskarray controller and a plurality of disk devices. Each of the disk devices has a media, a head, and a head position controller. The diskarray controller performs online data check operation, and stops the online data check operation over the disk device at first predetermined timing. After stopping the online data check operation, the diskarray controller issues an unload enable command to the disk device so as to move the head to a position different from positions at which the head reads or writes data from or to the media. The head position controller of the disk device moves the position of the head on the basis of the received unload enable command.

Abstract: A disk array system having a plurality of disk units includes an upper-level data transfer controller for controlling transfer of data to and from an upper-level apparatus, a data buffer for temporarily storing therein data from the upper-level apparatus, a drive data transfer controller for controlling the data transfer between the buffer and the units, and a main microprocessor for controlling the the transfer controllers. When transferring data, the microprocessor indicates an address to be used in the buffer and a distribution mode of data to the data transfer controllers so that the data transfer is conducted thereafter without intervention of the microprocessor. During the transfer, the microprocessor can generate information for a subsequent data transfer to indicate the information to the transfer controllers. After a data transfer is terminated, the pertinent transfer controller can immediately execute the next data transfer, which increases the utilization efficiency of the data bus.