Patents by Inventor Yoshinori Uezato
Yoshinori Uezato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11901272Abstract: A semiconductor module includes a ceramic board, a circuit pattern metal plate on a principal surface of the ceramic board, and an external connection terminal including a bonding portion and a conductive portion. The metal plate includes a bonding area at a first surface thereof, and a stress relaxation portion disposed within the bonding area. The bonding portion has a bonding surface, and an edge that is located at a position overlapping an area in which the stress relaxation portion is disposed in a plan view. A solder is disposed between the bonding surface and the bonding area, to bond the external connection terminal to the circuit pattern metal plate.Type: GrantFiled: December 28, 2020Date of Patent: February 13, 2024Assignee: FUJI ELECTRIC CO., LTD.Inventor: Yoshinori Uezato
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Publication number: 20230282601Abstract: The present invention provides a joining that suppresses ion migration and also has excellent corrosion resistance, high bonding strength, and high reliability at the joining, and a semiconductor device. The present invention provides semiconductor joinings comprising: at least two semiconductor constituent members; and silver-containing bonding material layers that bond the semiconductor constituent members, in which a corrosion inhibitor coating layer is provided in contact with the silver-containing bonding material layers, and a semiconductor device including the same.Type: ApplicationFiled: January 26, 2023Publication date: September 7, 2023Applicant: FUJI ELECTRIC CO., LTD.Inventors: Yoshinori UEZATO, Masanori TAKAZAWA, Shoichiro SAKAI
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Patent number: 11600541Abstract: A semiconductor module, including a ceramic board, a circuit pattern metal plate formed on a principal surface of the ceramic board, an external connection terminal bonded, via a solder, to the circuit pattern metal plate, and a low linear expansion coefficient metal plate located between the circuit pattern metal plate and the external connection terminal. The circuit pattern metal plate has a first edge portion and a second edge portion, which are opposite to each other and are respectively at a first side and a second side of the circuit pattern metal plate. The low linear expansion coefficient metal plate has a linear expansion coefficient lower than a linear expansion coefficient of the circuit pattern metal plate.Type: GrantFiled: December 28, 2020Date of Patent: March 7, 2023Assignee: FUJI ELECTRIC CO., LTD.Inventor: Yoshinori Uezato
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Patent number: 11521941Abstract: A semiconductor device including a semiconductor chip disposed on a substrate having a conductive pattern, an insulating plate and a metal plate that are sequentially formed and respectively have the thicknesses of T2, T1 and T3. The metal plate has a plurality of depressions formed on a rear surface thereof. In a side view, a first edge face, which is an edge face of the conductive pattern, is at a first distance away from a second edge face that is an edge face of the metal plate, and a third edge face, which is an edge face of the semiconductor chip, is at a second distance away from the second edge face. Each depression is located within a depression formation distance from the first edge face, where: 0<depression formation distance?(0.9×T12/first distance), and/or (1.1×T12/first distance)?depression formation distance<second distance.Type: GrantFiled: December 28, 2020Date of Patent: December 6, 2022Assignee: FUJI ELECTRIC CO., LTD.Inventors: Yoshinori Oda, Yoshinori Uezato
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Patent number: 11133271Abstract: In a semiconductor device, a first outer edge of a conductive pattern is located between the outermost edge of a first dimple and the innermost edge of a second dimple in a cross-sectional view of the device. When thermal stress due to temperature changes in the semiconductor device is applied to the ceramic circuit board, the first and second dimples suppress deformation of the ceramic circuit board that is caused due to the temperature changes. As a result, cracks in the ceramic circuit board and separation of the metal plate and the conductive pattern are prevented.Type: GrantFiled: February 25, 2020Date of Patent: September 28, 2021Assignee: FUJI ELECTRIC CO., LTD.Inventor: Yoshinori Uezato
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Publication number: 20210257268Abstract: A semiconductor module, including a ceramic board, a circuit pattern metal plate formed on a principal surface of the ceramic board, an external connection terminal bonded, via a solder, to the circuit pattern metal plate, and a low linear expansion coefficient metal plate located between the circuit pattern metal plate and the external connection terminal. The circuit pattern metal plate has a first edge portion and a second edge portion, which are opposite to each other and are respectively at a first side and a second side of the circuit pattern metal plate. The low linear expansion coefficient metal plate has a linear expansion coefficient lower than a linear expansion coefficient of the circuit pattern metal plate.Type: ApplicationFiled: December 28, 2020Publication date: August 19, 2021Applicant: FUJI ELECTRIC CO., LTD.Inventor: Yoshinori UEZATO
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Publication number: 20210257284Abstract: A semiconductor module includes a ceramic board, a circuit pattern metal plate on a principal surface of the ceramic board, and an external connection terminal including a bonding portion and a conductive portion. The metal plate includes a bonding area at a first surface thereof, and a stress relaxation portion disposed within the bonding area. The bonding portion has a bonding surface, and an edge that is located at a position overlapping an area in which the stress relaxation portion is disposed in a plan view. A solder is disposed between the bonding surface and the bonding area, to bond the external connection terminal to the circuit pattern metal plate.Type: ApplicationFiled: December 28, 2020Publication date: August 19, 2021Applicant: FUJI ELECTRIC CO., LTD.Inventor: Yoshinori UEZATO
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Publication number: 20210118822Abstract: A semiconductor device including a semiconductor chip disposed on a substrate having a conductive pattern, an insulating plate and a metal plate that are sequentially formed and respectively have the thicknesses of T2, T1 and T3. The metal plate has a plurality of depressions formed on a rear surface thereof. In a side view, a first edge face, which is an edge face of the conductive pattern, is at a first distance away from a second edge face that is an edge face of the metal plate, and a third edge face, which is an edge face of the semiconductor chip, is at a second distance away from the second edge face. Each depression is located within a depression formation distance from the first edge face, where: 0<depression formation distance?(0.9×T12/first distance), and/or (1.1×T12/first distance)?depression formation distance<second distance.Type: ApplicationFiled: December 28, 2020Publication date: April 22, 2021Applicant: FUJI ELECTRIC CO., LTD.Inventors: Yoshinori ODA, Yoshinori UEZATO
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Publication number: 20200194386Abstract: In a semiconductor device, a first outer edge of a conductive pattern is located between the outermost edge of a first dimple and the innermost edge of a second dimple in a cross-sectional view of the device. When thermal stress due to temperature changes in the semiconductor device is applied to the ceramic circuit board, the first and second dimples suppress deformation of the ceramic circuit board that is caused due to the temperature changes. As a result, cracks in the ceramic circuit board and separation of the metal plate and the conductive pattern are prevented.Type: ApplicationFiled: February 25, 2020Publication date: June 18, 2020Applicant: FUJI ELECTRIC CO., LTD.Inventor: Yoshinori UEZATO
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Patent number: 10607916Abstract: Provided is a substrate for semiconductor devices comprising: an insulating substrate; and a first metal board having a plurality of sides and formed on a first surface of the insulating substrate; wherein the first metal board includes: a corner portion positioned closer to a corner of a first side of the first metal board, for which a creepage distance between an edge of the first metal board and an edge of the insulating substrate reaches a smallest value for the first side; and a center portion positioned closer to a center of the first side than the corner portion, for which a creepage distance between the edge of the first metal board and the edge of the insulating substrate exceeds the smallest value; wherein a range of the center portion is larger than a range of the corner portion.Type: GrantFiled: January 30, 2017Date of Patent: March 31, 2020Assignee: FUJI ELECTRIC CO., LTD.Inventor: Yoshinori Uezato
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Patent number: 10541219Abstract: A base plate having concave curved portions (rearward-convex parts) curved in a rearward direction to be convex and have a predetermined curvature, is fixed to a surface of a cooling fin while being in contact with the surface of the cooling fin at vertices of the rearward-convex parts. A stacked substrate is bonded on a front surface of the base plate, at an area opposing the rearward-convex part. A spacer is provided on a rear surface of the base plate, at a position closer than an edge of a solder layer to a perimeter of the base plate. The spacer is sandwiched between the base plate and the cooling fin when a screw for fixing the base plate to the cooling fin is tightened and the spacer has a function of suppressing deformation of the base plate.Type: GrantFiled: April 2, 2018Date of Patent: January 21, 2020Assignee: FUJI ELECTRIC CO., LTD.Inventor: Yoshinori Uezato
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Patent number: 10262874Abstract: A semiconductor module radiator plate fabrication method includes soldering a plurality of insulating substrates of different shapes to a flat radiator plate, and forming a convex curve on an insulating substrate side of the radiator plate; obtaining a first concave curve by reversing the convex curve; setting a second concave curve on an insulating substrate side of a radiator plate after soldering, a bottom of the second concave curve being positioned under clearance between the plurality of insulating substrates; adding the first curve and the second curve to calculate a third concave curve on the insulating substrate side; and forming the third curve on a flat plate to form a radiator plate before soldering.Type: GrantFiled: September 26, 2016Date of Patent: April 16, 2019Assignee: FUJI ELECTRIC CO., LTD.Inventors: Yoshinori Uezato, Masayuki Soutome, Rikihiro Maruyama, Tomoaki Goto
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Publication number: 20180337153Abstract: A base plate having concave curved portions (rearward-convex parts) curved in a rearward direction to be convex and have a predetermined curvature, is fixed to a surface of a cooling fin while being in contact with the surface of the cooling fin at vertices of the rearward-convex parts. A stacked substrate is bonded on a front surface of the base plate, at an area opposing the rearward-convex part. A spacer is provided on a rear surface of the base plate, at a position closer than an edge of a solder layer to a perimeter of the base plate. The spacer is sandwiched between the base plate and the cooling fin when a screw for fixing the base plate to the cooling fin is tightened and the spacer has a function of suppressing deformation of the base plate.Type: ApplicationFiled: April 2, 2018Publication date: November 22, 2018Applicant: FUJI ELECTRIC CO., LTD.Inventor: Yoshinori UEZATO
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Publication number: 20170271236Abstract: Provided is a substrate for semiconductor devices comprising: an insulating substrate; and a first metal board having a plurality of sides and formed on a first surface of the insulating substrate; wherein the first metal board includes: a corner portion positioned closer to a corner of a first side of the first metal board, for which a creepage distance between an edge of the first metal board and an edge of the insulating substrate reaches a smallest value for the first side; and a center portion positioned closer to a center of the first side than the corner portion, for which a creepage distance between the edge of the first metal board and the edge of the insulating substrate exceeds the smallest value; wherein a range of the center portion is larger than a range of the corner portion.Type: ApplicationFiled: January 30, 2017Publication date: September 21, 2017Inventor: Yoshinori UEZATO
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Publication number: 20170011935Abstract: A semiconductor module radiator plate fabrication method includes soldering a plurality of insulating substrates of different shapes to a flat radiator plate, and forming a convex curve on an insulating substrate side of the radiator plate; obtaining a first concave curve by reversing the convex curve; setting a second concave curve on an insulating substrate side of a radiator plate after soldering, a bottom of the second concave curve being positioned under clearance between the plurality of insulating substrates; adding the first curve and the second curve to calculate a third concave curve on the insulating substrate side; and forming the third curve on a flat plate to form a radiator plate before soldering.Type: ApplicationFiled: September 26, 2016Publication date: January 12, 2017Applicant: FUJI ELECTRIC CO., LTD.Inventors: Yoshinori UEZATO, Masayuki SOUTOME, Rikihiro MARUYAMA, Tomoaki GOTO
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Publication number: 20130306296Abstract: When insulating substrates of different shapes are soldered to a radiator plate, a third concave curve is previously formed on an insulating substrate side of the radiator plate. The third curve is determined by adding a second concave curve which is expected at the time of actually soldering the insulating substrates to the radiator plate to a first concave curve obtained by moving upside down a convex curve which appears at the time of soldering the insulating substrates to a flat radiator plate. A bottom of the third curve is positioned under the large insulating substrate, and a curvature of a portion where the distance between the bottom and a reference point of the radiator plate is longer is made smaller than a curvature of a portion where the distance between the bottom and a reference point of the radiator plate is shorter.Type: ApplicationFiled: July 25, 2013Publication date: November 21, 2013Applicant: FUJI ELECTRIC CO., LTD.Inventors: Yoshinori Uezato, Masayuki Soutome, Rikihiro Maruyama, Tomoaki Goto