Patents by Inventor Yoshinosuke Nishijo

Yoshinosuke Nishijo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8810032
    Abstract: A method for manufacturing a semiconductor device, includes: forming a first metal layer on a semiconductor substrate, the semiconductor substrate including a diffusion layer; forming an insulating layer having an opening on the first metal layer; forming a second metal layer on the first metal layer in the opening of the insulating layer; removing the insulating layer; covering an exposed surface of the second metal layer with a third metal layer, the third metal layer including a metal having an ionization tendency lower than that of the second metal layer; and forming an electrode interconnect including the first metal layer, the second metal layer, and the third metal layer by removing the first metal layer using the third metal layer as a mask.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: August 19, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomomi Imamura, Tetsuo Matsuda, Yoshinosuke Nishijo
  • Patent number: 8415247
    Abstract: A method for manufacturing a semiconductor device, includes: forming a first metal layer on a semiconductor substrate, the semiconductor substrate including a diffusion layer; forming an insulating layer having an opening on the first metal layer; forming a second metal layer on the first metal layer in the opening of the insulating layer; removing the insulating layer; covering an exposed surface of the second metal layer with a third metal layer, the third metal layer including a metal having an ionization tendency lower than that of the second metal layer; and forming an electrode interconnect including the first metal layer, the second metal layer, and the third metal layer by removing the first metal layer using the third metal layer as a mask.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: April 9, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomomi Imamura, Tetsuo Matsuda, Yoshinosuke Nishijo
  • Publication number: 20120178223
    Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes a polishing step, a first amorphous silicon film formation step, a single crystallization step and a buffer layer formation step. In the first amorphous silicon film formation step, a first amorphous silicon film of the first conductivity type is formed on the polished back surface of the high-resistance layer, the first amorphous silicon film having a higher impurity concentration than the high-resistance layer. In the single crystallization step, the first amorphous silicon film is single-crystallized by irradiating the first amorphous silicon film with a first laser. In the buffer layer formation step, the formation and single-crystallization of the first amorphous silicon film are repeated more than once to form a buffer layer of the first conductivity type on the back surface of the high-resistance layer, the buffer layer having a higher impurity concentration than the high-resistance layer.
    Type: Application
    Filed: September 16, 2011
    Publication date: July 12, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yoshinosuke Nishijo, Hironobu Shibata, Hiroshi Ishibashi
  • Publication number: 20120001321
    Abstract: A method for manufacturing a semiconductor device, includes: forming a first metal layer on a semiconductor substrate, the semiconductor substrate including a diffusion layer; forming an insulating layer having an opening on the first metal layer; forming a second metal layer on the first metal layer in the opening of the insulating layer; removing the insulating layer; covering an exposed surface of the second metal layer with a third metal layer, the third metal layer including a metal having an ionization tendency lower than that of the second metal layer; and forming an electrode interconnect including the first metal layer, the second metal layer, and the third metal layer by removing the first metal layer using the third metal layer as a mask.
    Type: Application
    Filed: September 15, 2011
    Publication date: January 5, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tomomi IMAMURA, Tetsuo Natsuda, Yoshinosuke Nishijo
  • Patent number: 8067310
    Abstract: A method for manufacturing a semiconductor device, includes: forming a first metal layer on a semiconductor substrate, the semiconductor substrate including a diffusion layer; forming an insulating layer having an opening on the first metal layer; forming a second metal layer on the first metal layer in the opening of the insulating layer; removing the insulating layer; covering an exposed surface of the second metal layer with a third metal layer, the third metal layer including a metal having an ionization tendency lower than that of the second metal layer; and forming an electrode interconnect including the first metal layer, the second metal layer, and the third metal layer by removing the first metal layer using the third metal layer as a mask.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: November 29, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomomi Imamura, Tetsuo Matsuda, Yoshinosuke Nishijo
  • Publication number: 20100164095
    Abstract: A method for manufacturing a semiconductor device, includes: forming a first metal layer on a semiconductor substrate, the semiconductor substrate including a diffusion layer; forming an insulating layer having an opening on the first metal layer; forming a second metal layer on the first metal layer in the opening of the insulating layer; removing the insulating layer; covering an exposed surface of the second metal layer with a third metal layer, the third metal layer including a metal having an ionization tendency lower than that of the second metal layer; and forming an electrode interconnect including the first metal layer, the second metal layer, and the third metal layer by removing the first metal layer using the third metal layer as a mask.
    Type: Application
    Filed: December 23, 2009
    Publication date: July 1, 2010
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tomomi IMAMURA, Tetsuo MATSUDA, Yoshinosuke NISHIJO