Patents by Inventor Yoshio Fukasawa

Yoshio Fukasawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8503784
    Abstract: An image recognition apparatus recognizes the correspondence between character strings and logical elements composing a logical structure in an image in which the character strings are described as the logical elements to recognize each logical element.
    Type: Grant
    Filed: October 13, 2008
    Date of Patent: August 6, 2013
    Assignee: Fujitsu Limited
    Inventors: Hiroshi Tanaka, Yusaku Fujii, Hiroaki Takebe, Yoshinobu Hotta, Akihiro Minagawa, Noriaki Ozawa, Katsuhito Fujimoto, Yoshio Fukasawa, Masaki Inami, Kiichiro Watanabe
  • Publication number: 20090110282
    Abstract: An image recognition apparatus recognizes the correspondence between character strings and logical elements composing a logical structure in an image in which the character strings are described as the logical elements to recognize each logical element.
    Type: Application
    Filed: October 13, 2008
    Publication date: April 30, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Hiroshi Tanaka, Yusaku Fujii, Hiroaki Takebe, Yoshinobu Hotta, Akihiro Minagawa, Noriaki Ozawa, Katsuhito Fujimoto, Yoshio Fukasawa, Masaki Inami, Kiichiro Watanabe
  • Patent number: 6111984
    Abstract: Matching between a reference image and an input image is performed without relying on specific elements such as line segments or tables. An edge image is generated from the reference image and divided into small blocks, and search range and search priority of each small block are determined and stored in a storage device. When an input image is input, an edge image thereof is generated. The small blocks in the reference image are retrieved in order of priority, and matching with the input image is judged. When the corresponding position of one small block is determined, the search range and search priority for other small blocks not yet judged for matching are updated on the basis of the determined corresponding position.
    Type: Grant
    Filed: January 21, 1998
    Date of Patent: August 29, 2000
    Assignee: Fujitsu Limited
    Inventor: Yoshio Fukasawa
  • Patent number: 6074518
    Abstract: A plasma processing apparatus comprises a chamber, and an upper electrode and a lower electrode, parallelly provided in the chamber to oppose each other at a predetermined interval, for defining a plasma generation region between the electrodes. An object to be processed is mounted on the lower electrode. RF powers are supplied to the electrodes, so that a plasma generates between the electrodes, thereby performing a plasma process with respect to the object to be processed. A cylindrical ground electrode is provided around the plasma generation region in the chamber, for enclosing the plasma in the plasma generation region, and has a plurality of through holes for passing a process gas.
    Type: Grant
    Filed: January 4, 1999
    Date of Patent: June 13, 2000
    Assignees: Tokyo Electron Limited, Tokyo Electron Yamanashi Limited
    Inventors: Kosuke Imafuku, Shosuke Endo, Kazuhiro Tahara, Hiroshi Tsuchiya, Masayuki Tomoyasu, Yukio Naito, Kazuya Nagaseki, Ryo Nonaka, Keizo Hirose, Yoshio Fukasawa, Akira Koshiishi, Isao Kobayashi
  • Patent number: 5716534
    Abstract: A plasma etching apparatus includes a process chamber that can be set at a reduced pressure. A lower electrode on which a semiconductor wafer is placed and an upper electrode opposing the lower electrode are disposed in the process chamber. The lower and upper electrodes are connected to RF power supplies, respectively. First and second RF powers, the phases and power ratio of which are separately controlled, can be applied to the upper and lower electrodes. Parameters including the frequencies, power values, and relative phases of the first and second RF powers are selected in order to set the etching characteristics, e.g., an etching rate, the planar uniformity of the etching rate, the etching selectivity ratio and the like to predetermined values. During etching, the first and second RF powers are monitored by separate detectors, and are maintained at initial preset values through a controller.
    Type: Grant
    Filed: November 29, 1995
    Date of Patent: February 10, 1998
    Assignee: Tokyo Electron Limited
    Inventors: Hiroshi Tsuchiya, Yoshio Fukasawa, Shuji Mochizuki, Yukio Naito, Kosuke Imafuku
  • Patent number: 5611655
    Abstract: A vacuum process apparatus includes a convey chamber having a plurality of loading/unloading ports and an airtight structure kept in a vacuum when a target object is conveyed, at least one preliminary vacuum chamber connected to the convey chamber through a loading/unloading port, a plurality of vacuum process chambers connected to the convey chamber through the loading/unloading ports and each having a vacuum process mechanism, a plurality of gate valves for opening/closing the plurality of loading/unloading ports, and a multi-joint arm member, arranged in the convey chamber, for conveying the target object between the convey chamber and the vacuum process chambers, and between the convey chamber and the preliminary chamber. The convey chamber is evacuated through a bearing for a pivot shaft of the multi-joint arm member.
    Type: Grant
    Filed: January 4, 1996
    Date of Patent: March 18, 1997
    Assignees: Tokyo Electron Limited, Tokyo Electron Yamanashi Limited
    Inventors: Yoshio Fukasawa, Shozo Hosoda, Tatsuya Nakagome, Takashi Tozawa, Koji Suzuki, Yasumasa Ishihara, Minoru Aoyagi, Mahito Kajihara
  • Patent number: 5560804
    Abstract: In plasma-etching a polysilicon layer of a semiconductor wafer where the polysilicon layer is formed on an SiO.sub.2 film, plasma of a processing gas including a halogen element containing gas and a gas containing oxygen or nitrogen is generated, and a predetermined portion of the polysilicon layer is selectively exposed in plasma, thereby etching the portion.
    Type: Grant
    Filed: January 30, 1995
    Date of Patent: October 1, 1996
    Assignees: Tokyo Electron Limited, Tokyo Electron Yamanashi Limited
    Inventors: Fumihiko Higuchi, Yoshio Fukasawa
  • Patent number: 5314573
    Abstract: The present invention provides a dry etching method for achieving a satisfactory anisotropic etching of, for example, a semiconductor wafer, particularly, a polysilicon layer formed on the wafer. In the present invention, a mixed gas comprising a first gas containing Br and a second gas containing a halogen element other than Br, e.g., a mixed gas consisting of a HBr gas and a HCl gas, is introduced into a vacuum chamber. The mixed gas is converted into plasma by applying a high frequency power to an upper electrode 5. The plasma region is irradiated, as desired, with an ultraviolet light. The semiconductor wafer is etched with the plasma. The etching is carried out under optimum conditions. For example, the surface temperature of the semiconductor wafer, i.e., workpiece, is maintained at a level falling within a range of between 70.degree. C. and 120.degree. C. Also, the flow rate ratio of the mixed gas is suitably controlled.
    Type: Grant
    Filed: May 20, 1992
    Date of Patent: May 24, 1994
    Assignee: Tokyo Electron Limited
    Inventors: Fumihiko Higuchi, Yoshio Fukasawa
  • Patent number: 5246529
    Abstract: A workpiece is etched with a plasma. First, a chamber is provided in which a pair of electrodes are arranged parallel to each other at a distance. The electrodes define a plasma generation area therebetween. The workpiece is arranged in the chamber. The chamber is evacuated, and a desired plasma generation gas is introduced into the plasma generation area. Light having a wavelength of not more than 436 nm is radiated onto the gas in the plasma generation area for a predetermined period of time. Then, a high-frequency power is applied across the electrodes to generate a plasma from the plasma generation gas. The workpiece is etched with the generated plasma.
    Type: Grant
    Filed: September 5, 1991
    Date of Patent: September 21, 1993
    Assignee: Tokyo Electron Limited
    Inventors: Yoshio Fukasawa, Kenji Momose