Abstract: Provided is a susceptor 13 for manufacturing an epitaxial wafer, comprising a mesh-like groove 13b on a mount face on which a silicon substrate W is to be mounted, wherein a coating H of silicon carbide is formed on the mount face, and the coating has a surface roughness of 1 ?m or more in centerline average roughness Ra and a maximum height of a protrusion 13p generated in forming the coating H of 5 ?m or less. Thus, defects such as warping and slip as well as adhesion of the silicon substrate to the susceptor are prevented.

Abstract: Provided is a susceptor 13 for manufacturing an epitaxial wafer, comprising a mesh-like groove 13b on a mount face on which a silicon substrate W is to be mounted, wherein a coating H of silicon carbide is formed on the mount face, and the coating has a surface roughness of 1 ?m or more in centerline average roughness Ra and a maximum height of a protrusion 13p generated in forming the coating H of 5 ?m or less. Thus, defects such as warping and slip as well as adhesion of the silicon substrate to the susceptor are prevented.

Abstract: A silica-based interlayer insulating layer having a low dielectric constant is formed with SOG material on a substrate, in which a wiring-layer forming space is then formed. If necessary, a UV ray irradiation is performed under an oxidizing atmosphere. A Si—OH bond is formed on a surface of the insulating layer. A monomolecular layer film is then adhered to the inner surface of the space, which is then modified to be a catalyst with a solution containing Pd compound. On the catalyst monomolecular layer, a copper-diffusion-resistant film is formed by electroless plating, on which a copper plate is then formed as a wiring layer.

Abstract: A silica-based coating film having a low dielectric constant not exceeding 2.5 can be formed on the surface of a substrate to serve as a planarizing layer or an interlayer insulating layer by coating the surface with a unique coating solution containing a hydrolysis-condensation product of a polyalkoxy silane compound such as tetraethoxy silane and monomethyl trimethoxy silane, which is formed by the hydrolysis of a polyalkoxy silane in the presence of a basic catalyst such as ammonia in an alcohol solvent in a relatively low concentration followed by replacement of the alcohol solvent with an aprotic polar solvent such as N-methyl pyrrolidone, followed by drying and baking at 350 to 800° C.

Abstract: In a method for forming a wiring using a dual damascene process in which a multilayer wiring structure is formed by embedding a first etching space formed in an interlayer insulating layer and a second etching space which communicates thereto with a conductor material, a number of steps may be reduced and flexibility in the step management is enhanced without deteriorating a low dielectric material layer which constitutes the interlayer insulating layer. Therefor, a filler material whose major ingredient is a spin-on-glass material capable of being easily removed by a stripping solution which gives no damage to the interlayer insulating layer is used as a material filled in the first etching space in order to protect a lower wiring layer from exposure light to form a photoresist pattern for forming the second etching space. Furthermore, no light absorbing material for absorbing the exposure light is added to this filler material.

Abstract: For suppressing decomposition of an organic group (for example, a CH3 group) which is bonded to an Si atom of an organic SOG film for use in a flattening process at the time of an ashing process, there is provided a method comprising the steps of: forming an organic SOG layer directly on a lower wiring layer or on a predetermined film including a hillock protection layer which is formed on the lower wiring layer in advance; forming an upper wiring layer on the organic SOG layer without using an etching back process; forming a via hole through an etching process by using a patterned resist layer provided on the upper wiring layer as a mask; performing an ashing process with a plasma by making ions or radicals which are induced from oxygen gas as a main reactant, under an atmospheric pressure ranging from 0.01 Torr to 30.0 Torr; and filling said via hole with a conductive material so as to electrically connect the lower wiring layer to the upper wiring layer.

Abstract: A silica-based coating film having a low dielectric constant not exceeding 2.5 can be formed on the surface of a substrate to serve as a planarizing layer or an interlayer insulating layer by coating the surface with a unique coating solution containing a hydrolysis-condensation product of a polyalkoxy silane compound such as tetraethoxy silane and monomethyl trimethoxy silane, which is formed by the hydrolysis of a polyalkoxy silane in the presence of a basic catalyst such as ammonia in an alcohol solvent in a relatively low concentration followed by replacement of the alcohol solvent with an aprotic polar solvent such as N-methyl pyrrolidone, followed by drying and baking at 350 to 800° C.

Abstract: An undercoating layer material for lithography, containing polysiloxane and an organotitanium compound having no alkoxy group; and a method for forming a wiring including a step of applying the undercoating layer material onto a substrate and curing to form an undercoating layer and forming a photoresist layer thereon; a step of removing by dry etching the exposed portion of the undercoating layer which is not covered with the photoresist pattern; a step of forming a predetermined wiring pattern using the photoresist pattern and the patterned undercoating layer as masks; and a step of removing the undercoating layer and photoresist pattern remaining on the substrate. The undercoating layer material is advantageous that the storage stability, the form of the lower portion of the resist pattern, and the burying properties are excellent and no voids are found.

Abstract: A silica-based interlayer insulating layer having a low dielectric constant is formed with SOG material on a substrate, in which a wiring-layer forming space is then formed. If necessary, a UV ray irradiation is performed under an oxidizing atmosphere. A Si—OH bond is formed on a surface of the insulating layer. A monomolecular layer film is then adhered to the inner surface of the space, which is then modified to be a catalyst with a solution containing Pd compound. On the catalyst monomolecular layer, a copper-diffusion-resistant film is formed by electroless plating, on which a copper plate is then formed as a wiring layer.

Abstract: A silica-based coating film having a low dielectric constant not exceeding 2.5 can be formed on the surface of a substrate to serve as a planarizing layer or an interlayer insulating layer by coating the surface with a unique coating solution containing a hydrolysis-condensation product of a polyalkoxy silane compound such as tetraethoxy silane and monomethyl trimethoxy silane, which is formed by the hydrolysis of a polyalkoxy silane in the presence of a basic catalyst such as ammonia in an alcohol solvent in a relatively low concentration followed by replacement of the alcohol solvent with an aprotic polar solvent such as N-methyl pyrrolidone, followed by drying and baking at 350 to 800° C.

Abstract: For suppressing decomposition of an organic group (for example, a CH3 group) which is bonded to an Si atom of an organic SOG film for use in a flattening process at the time of an ashing process, there is provided a method comprising the steps of: forming an organic SOG layer directly on a lower wiring layer or on a predetermined film including a hillock protection layer which is formed on the lower wiring layer in advance; forming an upper wiring layer on the organic SOG layer without using an etching back process; forming a via hole through an etching process by using a patterned resist layer provided on the upper wiring layer as a mask; performing an ashing process with a plasma by making ions or radicals which are induced from oxygen gas as a main reactant, under an atmospheric pressure ranging from 0.01 Torr to 30.0 Torr; and filling said via hole with a conductive material so as to electrically connect the lower wiring layer to the upper wiring layer.

Abstract: A method for suppressing the cutting of bonds between organic radical (for example, CH3-radical) or H-radical and Si atom in SOG film during an ashing process, thereby maintaining a low dielectric constant, after wiring gutters are formed through etching on organic or inorganic SOG film of low dielectric constant using a patterned resist film(s) thereon as a mask, the resist film(s) is removed by treating with the ashing process by use of a plasma ashing apparatus of a sheet-fed down-stream type under an atmospheric pressure of 1.2 Torr, for example, and thereafter barrier metal is formed and Cu is filled into the wiring gutters, so as to form the wiring.

Abstract: For suppressing decomposition of an organic group (for example, a CH3 group) which is bonded to an Si atom of an organic SOG film for use in a flattening process at the time of an ashing process, there is provided a method comprising the steps of: forming an organic SOG layer directly on a lower wiring layer or on a predetermined film including a hillock protection layer which is formed on the lower wiring layer in advance; forming an upper wiring layer on the organic SOG layer without using an etching back process; forming a via hole through an etching process by using a patterned resist layer provided on the upper wiring layer as a mask; performing an ashing process with a plasma by making ions or radicals which are induced from oxygen gas as a main reactant, under an atmospheric pressure ranging from 0.01 Torr to 30.0 Torr; and filling said via hole with a conductive material so as to electrically connect the lower wiring layer to the upper wiring layer.

Abstract: For suppressing decomposition of organic group (for example, CH3 group) during ashing process, which is bonded to Si atom of an organic SOG film or layer for use in flattening process, a method comprises following steps: forming an organic SOG layer directly or through a predetermined film including a hillock protection layer on said lower wiring layer; forming said upper wiring layer on said organic SOG layer without processing of etching back; forming a via hole through an etching process by using a patterned resist layer provided on said upper wiring layer as a mask; performing ashing process with a plasma by making ion or radical which is induced from oxygen gas as a main reactant, under an atmosphere of pressure ranging from 0.01 Torr to 30.0 Torr; and burying said via hole with conductive material so as to electrically connect between said lower wiring layer and said upper wiring layer.

Abstract: An anti-reflective coating-forming composition comprising: (A) at least one compound selected from the group consisting of (i) a compound represented by the following formula (1): Si(OR1)a(OR2)b(OR3)c(OR4)d  (1) (ii) a compound represented by the following formula (2): R5Si(OR6)e(OR7)f(OR8)g  (2) and (iii) a compound represented by the following formula (3): R9R10Si(OR11)h(OR12)I  (3) and (B) a thermosetting resin which can be condensed to said component (A) and has an absorption capacity with respect to exposing light.

Abstract: For suppressing decomposition of organic group (for example, CH3 group) during ashing process, which is bonded to Si atom of an organic SOG film or layer for use in flattening process, a method comprises following steps: forming an organic SOG layer directly or through a predetermined film including a hillock protection layer on said lower wiring layer; forming said upper wiring layer on said organic SOG layer without processing of etching back; forming a via hole through an etching process by using a patterned resist layer provided on said upper wiring layer as a mask; performing ashing process with a plasma by making ion or radical which is induced from oxygen gas as a main reactant, under an atmosphere of pressure ranging from 0.01 Torr to 30.0 Torr; and burying said via hole with conductive material so as to electrically connect between said lower wiring layer and said upper wiring layer.

Abstract: Disclosed is a method for the formation of a silica coating film having a remarkably high crack-forming thickness limit on the surface of a substrate which may be highly heat resistant, for example, having a circuit wiring layer of polycrystalline silicon to withstand a temperature higher than 500° C. without excessive diffusion of dopant through the source layer or drain layer of the semiconductor device. The method comprises the steps of: coating the substrate surface with a coating solution containing a modified polysilazane which is a reaction product of a polysilazane and a dialkyl alkanol amine, drying the coating layer, subjecting the coating layer to a first baking treatment at 350-450° C. for 10-60 minutes and subjecting the layer to a second baking treatment at 550-800° C. for 0.5-60 minutes.

Abstract: An anti-reflective coating-forming composition comprising: (A) at least one compound selected from the group consisting of (i) a compound represented by the following formula (1):

Abstract: A substrate onto which a coating solution is dropped is rotated at a low speed in a first rotational mode and then after an interval of time at a high speed in a second rotational mode. At the end of the first rotational mode, the coating solution is coated to a thickness larger than a given thickness on irregularities on the substrate such as twin patterns and a global pattern, with the coating solution being coated to a thickness smaller than the given thickness between the twin patterns. Subsequently, at the start of the second rotational mode, the coating solution coated on the twin patterns and the global pattern flows into spaces between these patterns. At the end of the second rotational mode, the thickness of the coating solution on the twin patterns is almost nil, and the thickness of the coating solution on the global pattern is small in its entirety though it is somewhat large in the central area of the global pattern.

Abstract: Disclosed is a method for the formation of a silica coating film having a remarkably high crack-forming thickness limit on the surface of a substrate which may be highly heat resistant, for example, having a circuit wiring layer of polycrystalline silicon to withstand a temperature higher than 500° C. without excessive diffusion of dopant through the source layer or drain layer of the semiconductor device. The method comprises the steps of: coating the substrate surface with a coating solution containing a modified polysilazane which is a reaction product of a polysilazane and a dialkyl alkanol amine, drying the coating layer, subjecting the coating layer to a first baking treatment at 350-450° C. for 10-60 minutes and subjecting the layer to a second baking treatment at 550-800° C. for 0.5-60 minutes.